508 	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);  in update_turbo_state()
950 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);  in set_power_ctl_ee_state()
1343 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);  in show_energy_efficiency()
1477 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);  in atom_get_min_pstate()
1485 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);  in atom_get_max_pstate()
1493 	rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);  in atom_get_turbo_pstate()
1528 	rdmsrl(MSR_FSB_FREQ, value);  in silvermont_get_scaling()
1544 	rdmsrl(MSR_FSB_FREQ, value);  in airmont_get_scaling()
1555 	rdmsrl(MSR_ATOM_CORE_VIDS, value);  in atom_get_vid()
1563 	rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);  in atom_get_vid()
1571 	rdmsrl(MSR_PLATFORM_INFO, value);  in core_get_min_pstate()
1579 	rdmsrl(MSR_PLATFORM_INFO, value);  in core_get_max_pstate_physical()
1624 	rdmsrl(MSR_PLATFORM_INFO, plat_info);  in core_get_max_pstate()
1656 	rdmsrl(MSR_TURBO_RATIO_LIMIT, value);  in core_get_turbo_pstate()
1690 	rdmsrl(MSR_TURBO_RATIO_LIMIT, value);  in knl_get_turbo_pstate()
1877 	rdmsrl(MSR_IA32_APERF, aperf);  in intel_pstate_sample()
1878 	rdmsrl(MSR_IA32_MPERF, mperf);  in intel_pstate_sample()
2969 		rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);  in intel_pstate_platform_pwr_mgmt_exists()
3026 	rdmsrl(MSR_PM_ENABLE, value);  in intel_pstate_hwp_is_enabled()