Lines Matching refs:tcaddr
41 static void __iomem *tcaddr; variable
60 upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)); in tc_get_cycles()
61 lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles()
62 } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV))); in tc_get_cycles()
70 return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles32()
78 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_suspend()
79 tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR)); in tc_clksrc_suspend()
80 tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC)); in tc_clksrc_suspend()
81 tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) & in tc_clksrc_suspend()
85 bmr_cache = readl(tcaddr + ATMEL_TC_BMR); in tc_clksrc_suspend()
94 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_resume()
95 writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC)); in tc_clksrc_resume()
96 writel(0, tcaddr + ATMEL_TC_REG(i, RA)); in tc_clksrc_resume()
97 writel(0, tcaddr + ATMEL_TC_REG(i, RB)); in tc_clksrc_resume()
99 writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR)); in tc_clksrc_resume()
101 writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER)); in tc_clksrc_resume()
104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
108 writel(bmr_cache, tcaddr + ATMEL_TC_BMR); in tc_clksrc_resume()
110 writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); in tc_clksrc_resume()
208 writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); in tc_set_periodic()
221 writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC)); in tc_next_event()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
320 tcaddr + ATMEL_TC_REG(0, CMR)); in tcb_setup_dual_chan()
321 writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); in tcb_setup_dual_chan()
322 writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); in tcb_setup_dual_chan()
323 writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ in tcb_setup_dual_chan()
324 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
330 tcaddr + ATMEL_TC_REG(1, CMR)); in tcb_setup_dual_chan()
331 writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ in tcb_setup_dual_chan()
332 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
335 writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); in tcb_setup_dual_chan()
337 writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); in tcb_setup_dual_chan()
346 tcaddr + ATMEL_TC_REG(0, CMR)); in tcb_setup_single_chan()
347 writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ in tcb_setup_single_chan()
348 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
351 writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); in tcb_setup_single_chan()
387 if (tcaddr) in tcb_clksrc_init()
455 tcaddr = tc.regs; in tcb_clksrc_init()
506 tcaddr = NULL; in tcb_clksrc_init()