1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7  * Exynos4 MCT(Multi-Core Timer) support
147 	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);  in exynos4_mct_write()
161  * exynos4_read_count_64 - Read all 64-bits of the global counter
163  * This will read all 64-bits of the global counter taking care to make sure
164  * that the upper and lower half match.  Note that reading the MCT can be quite
165  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
185  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
187  * This will read just the lower 32-bits of the global counter.  This is marked
208 	.name		= "mct-frc",
227 			 "cycles_t needs to move to 32-bit for ARM64 usage");  in exynos4_read_current_timer()
301 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in mct_set_state_periodic()
302 			    >> evt->shift);  in mct_set_state_periodic()
309 	.name			= "mct-comp",
327 	evt->event_handler(evt);  in exynos4_mct_comp_isr()
352 	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;  in exynos4_mct_tick_stop()
371 	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);  in exynos4_mct_tick_start()
373 	/* enable MCT tick interrupt */  in exynos4_mct_tick_start()
374 	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);  in exynos4_mct_tick_start()
376 	tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
379 	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
384 	/* Clear the MCT tick interrupt */  in exynos4_mct_tick_clear()
385 	if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)  in exynos4_mct_tick_clear()
386 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_tick_clear()
415 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in set_state_periodic()
416 			    >> evt->shift);  in set_state_periodic()
425 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_tick_isr()
429 	 * Mct would generate interrupt periodically  in exynos4_mct_tick_isr()
432 	if (!clockevent_state_periodic(&mevt->evt))  in exynos4_mct_tick_isr()
437 	evt->event_handler(evt);  in exynos4_mct_tick_isr()
446 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_starting_cpu()
448 	mevt->base = EXYNOS4_MCT_L_BASE(cpu);  in exynos4_mct_starting_cpu()
449 	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);  in exynos4_mct_starting_cpu()
451 	evt->name = mevt->name;  in exynos4_mct_starting_cpu()
452 	evt->cpumask = cpumask_of(cpu);  in exynos4_mct_starting_cpu()
453 	evt->set_next_event = exynos4_tick_set_next_event;  in exynos4_mct_starting_cpu()
454 	evt->set_state_periodic = set_state_periodic;  in exynos4_mct_starting_cpu()
455 	evt->set_state_shutdown = set_state_shutdown;  in exynos4_mct_starting_cpu()
456 	evt->set_state_oneshot = set_state_shutdown;  in exynos4_mct_starting_cpu()
457 	evt->set_state_oneshot_stopped = set_state_shutdown;  in exynos4_mct_starting_cpu()
458 	evt->tick_resume = set_state_shutdown;  in exynos4_mct_starting_cpu()
459 	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;  in exynos4_mct_starting_cpu()
460 	evt->rating = 500;	/* use value higher than ARM arch timer */  in exynos4_mct_starting_cpu()
462 	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);  in exynos4_mct_starting_cpu()
466 		if (evt->irq == -1)  in exynos4_mct_starting_cpu()
467 			return -EIO;  in exynos4_mct_starting_cpu()
469 		irq_force_affinity(evt->irq, cpumask_of(cpu));  in exynos4_mct_starting_cpu()
470 		enable_irq(evt->irq);  in exynos4_mct_starting_cpu()
484 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_dying_cpu()
486 	evt->set_state_shutdown(evt);  in exynos4_mct_dying_cpu()
488 		if (evt->irq != -1)  in exynos4_mct_dying_cpu()
489 			disable_irq_nosync(evt->irq);  in exynos4_mct_dying_cpu()
490 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_dying_cpu()
503 		panic("%s: unable to ioremap mct address space\n", __func__);  in exynos4_timer_resources()
510 	mct_clk = of_clk_get_by_name(np, "mct");  in exynos4_timer_resources()
512 		panic("%s: unable to retrieve mct clock instance\n", __func__);  in exynos4_timer_resources()
535 		pr_err("exynos-mct: too many (%d) interrupts configured in DT\n",  in exynos4_timer_interrupts()
545 					 exynos4_mct_tick_isr, "MCT",  in exynos4_timer_interrupts()
547 		WARN(err, "MCT: can't request IRQ %d (%d)\n",  in exynos4_timer_interrupts()
555 			pcpu_mevt->evt.irq = -1;  in exynos4_timer_interrupts()
564 					pcpu_mevt->name, pcpu_mevt)) {  in exynos4_timer_interrupts()
565 				pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",  in exynos4_timer_interrupts()
570 			pcpu_mevt->evt.irq = mct_irq;  in exynos4_timer_interrupts()
592 			if (pcpu_mevt->evt.irq != -1) {  in exynos4_timer_interrupts()
593 				free_irq(pcpu_mevt->evt.irq, pcpu_mevt);  in exynos4_timer_interrupts()
594 				pcpu_mevt->evt.irq = -1;  in exynos4_timer_interrupts()
630 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
631 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);