48 static void __iomem *gt_base;  variable
67 	upper = readl_relaxed(gt_base + GT_COUNTER1);  in _gt_counter_read()
70 		lower = readl_relaxed(gt_base + GT_COUNTER0);  in _gt_counter_read()
71 		upper = readl_relaxed(gt_base + GT_COUNTER1);  in _gt_counter_read()
100 	writel_relaxed(ctrl, gt_base + GT_CONTROL);  in gt_compare_set()
101 	writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);  in gt_compare_set()
102 	writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);  in gt_compare_set()
105 		writel_relaxed(delta, gt_base + GT_AUTO_INC);  in gt_compare_set()
110 	writel_relaxed(ctrl, gt_base + GT_CONTROL);  in gt_compare_set()
117 	ctrl = readl(gt_base + GT_CONTROL);  in gt_clockevent_shutdown()
120 	writel(ctrl, gt_base + GT_CONTROL);  in gt_clockevent_shutdown()
141 	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &  in gt_clockevent_interrupt()
159 	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);  in gt_clockevent_interrupt()
204 	ctrl = readl(gt_base + GT_CONTROL);  in gt_resume()
207 		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);  in gt_resume()
228 	return readl_relaxed(gt_base + GT_COUNTER0);  in gt_read_long()
243 	writel(0, gt_base + GT_CONTROL);  in gt_clocksource_init()
244 	writel(0, gt_base + GT_COUNTER0);  in gt_clocksource_init()
245 	writel(0, gt_base + GT_COUNTER1);  in gt_clocksource_init()
247 	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);  in gt_clocksource_init()
277 	gt_base = of_iomap(np, 0);  in global_timer_of_register()
278 	if (!gt_base) {  in global_timer_of_register()
332 	iounmap(gt_base);  in global_timer_of_register()