Lines Matching +full:multi +full:- +full:system

1 # SPDX-License-Identifier: GPL-2.0-only
167 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
188 	  Support for Multi Timer Unit. MTU provides access
190 	  32-bit free running decrementing counters.
244 	bool "Integrator-AP timer driver" if COMPILE_TEST
247 	  Enables support for the Integrator-AP timer.
280 	  available on many OMAP-like platforms.
289 	  It has a 64-bit counter with update rate up to 1000MHz.
290 	  This counter is accessed via couple of 32-bit memory-mapped registers.
309 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
313 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
318 	bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
322 	  This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
340 	  power-of-2 divisor of the clock rate. The behaviour can also be
343 	  The main use of the event stream is wfe-based timeouts of userspace
354 	bool "Workaround for Freescale/NXP Erratum A-008585"
360 	  A-008585 ("ARM generic timer may contain an erroneous
362 	  fsl,erratum-a008585 property is found in the timer node.
371 	  161010101. The workaround will be active if the hisilicon,erratum-161010101
375 	bool "Workaround for Cortex-A73 erratum 858921"
380 	  This option enables a workaround applicable to Cortex-A73
393 	  allwinner,erratum-unknown1 property is found in the timer node.
416 	bool "Support for the ARMv7M system time" if COMPILE_TEST
420 	  This option enables support for the ARMv7M system timer unit.
445 	bool "Exynos multi core timer driver" if COMPILE_TEST
448 	  Support for Multi Core Timer controller on Exynos SoCs.
509 	bool "J-Core PIT timer driver" if COMPILE_TEST
515 	  the integrated PIT in the J-Core synthesizable, open source SoC.
523 	  the Compare Match Timer (CMT) hardware available in 16/32/48-bit
531 	  This enables build of a clockevent driver for the Multi-Function
533 	  This hardware comes with 16-bit timer registers.
548 	  the 32-bit Timer Unit (TMU) hardware available on a wide range
557 	  the 48-bit System Timer (STI) hardware available on a SoCs
575 	  counter available in the "System Registers" block of
593 	bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
597 	  This enables OST0 support available on PXA and SA-11x0
635 	bool "i.MX system counter timer" if COMPILE_TEST
638 	  Enable this option to use i.MX system counter timer as a
660 	bool "Timer for the RISC-V platform" if COMPILE_TEST
665 	  This enables the per-hart timer built into all RISC-V systems, which
667 	  required for all RISC-V systems.
670 	bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
675 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
676 	  driver is usually used for NoMMU RISC-V systems.
679 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
683 	  Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
684 	  system.
685 	  csky,mptimer is not only used in SMP system, it also could be used in
686 	  single core system. It's not a mmio reg and it uses mtcr/mfcr instruction.
689 	bool "Gx6605s SOC system timer driver" if COMPILE_TEST
732 	  Support for the Operating System Timer of the Ingenic JZ SoCs.
741 	  based system. It supports the oneshot, the periodic