Lines Matching refs:clk_register_divider

138 	clk = clk_register_divider(NULL, div0_name, mux_name,  in zynq_clk_register_fclk()
142 	clk = clk_register_divider(NULL, div1_name, div0_name,  in zynq_clk_register_fclk()
195 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,  in zynq_clk_register_periph_clk()
283 	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,  in zynq_clk_setup()
327 	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,  in zynq_clk_setup()
333 	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,  in zynq_clk_setup()
340 	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,  in zynq_clk_setup()
343 	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",  in zynq_clk_setup()
391 	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,  in zynq_clk_setup()
394 	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",  in zynq_clk_setup()
416 	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,  in zynq_clk_setup()
419 	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",  in zynq_clk_setup()
448 	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,  in zynq_clk_setup()
451 	clk = clk_register_divider(NULL, "can_div1", "can_div0",  in zynq_clk_setup()
488 	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,  in zynq_clk_setup()