Lines Matching +full:0 +full:x04a00000
17 #define TOP_CLK_MUX0 0x04
18 #define TOP_CLK_MUX1 0x08
19 #define TOP_CLK_MUX2 0x0c
20 #define TOP_CLK_MUX3 0x10
21 #define TOP_CLK_MUX4 0x14
22 #define TOP_CLK_MUX5 0x18
23 #define TOP_CLK_MUX6 0x1c
24 #define TOP_CLK_MUX7 0x20
25 #define TOP_CLK_MUX9 0x28
28 #define TOP_CLK_GATE0 0x34
29 #define TOP_CLK_GATE1 0x38
30 #define TOP_CLK_GATE2 0x3c
31 #define TOP_CLK_GATE3 0x40
32 #define TOP_CLK_GATE4 0x44
33 #define TOP_CLK_GATE5 0x48
34 #define TOP_CLK_GATE6 0x4c
36 #define TOP_CLK_DIV0 0x58
38 #define PLL_CPU_REG 0x80
39 #define PLL_VGA_REG 0xb0
40 #define PLL_DDR_REG 0xa0
43 #define LSP0_TIMER3_CLK 0x4
44 #define LSP0_TIMER4_CLK 0x8
45 #define LSP0_TIMER5_CLK 0xc
46 #define LSP0_UART3_CLK 0x10
47 #define LSP0_UART1_CLK 0x14
48 #define LSP0_UART2_CLK 0x18
49 #define LSP0_SPIFC0_CLK 0x1c
50 #define LSP0_I2C4_CLK 0x20
51 #define LSP0_I2C5_CLK 0x24
52 #define LSP0_SSP0_CLK 0x28
53 #define LSP0_SSP1_CLK 0x2c
54 #define LSP0_USIM0_CLK 0x30
55 #define LSP0_GPIO_CLK 0x34
56 #define LSP0_I2C3_CLK 0x38
59 #define LSP1_UART4_CLK 0x08
60 #define LSP1_UART5_CLK 0x0c
61 #define LSP1_PWM_CLK 0x10
62 #define LSP1_I2C2_CLK 0x14
63 #define LSP1_SSP2_CLK 0x1c
64 #define LSP1_SSP3_CLK 0x20
65 #define LSP1_SSP4_CLK 0x24
66 #define LSP1_USIM1_CLK 0x28
69 #define AUDIO_I2S0_DIV_CFG1 0x10
70 #define AUDIO_I2S0_DIV_CFG2 0x14
71 #define AUDIO_I2S0_CLK 0x18
72 #define AUDIO_I2S1_DIV_CFG1 0x20
73 #define AUDIO_I2S1_DIV_CFG2 0x24
74 #define AUDIO_I2S1_CLK 0x28
75 #define AUDIO_I2S2_DIV_CFG1 0x30
76 #define AUDIO_I2S2_DIV_CFG2 0x34
77 #define AUDIO_I2S2_CLK 0x38
78 #define AUDIO_I2S3_DIV_CFG1 0x40
79 #define AUDIO_I2S3_DIV_CFG2 0x44
80 #define AUDIO_I2S3_CLK 0x48
81 #define AUDIO_I2C0_CLK 0x50
82 #define AUDIO_SPDIF0_DIV_CFG1 0x60
83 #define AUDIO_SPDIF0_DIV_CFG2 0x64
84 #define AUDIO_SPDIF0_CLK 0x68
85 #define AUDIO_SPDIF1_DIV_CFG1 0x70
86 #define AUDIO_SPDIF1_DIV_CFG2 0x74
87 #define AUDIO_SPDIF1_CLK 0x78
88 #define AUDIO_TIMER_CLK 0x80
89 #define AUDIO_TDM_CLK 0x90
90 #define AUDIO_TS_CLK 0xa0
95 PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
96 PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
97 PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
98 PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
102 PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */
103 PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */
104 PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */
105 PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600@72 */
106 PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600@85 */
107 PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768@60 */
108 PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720@60 */
109 PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768@70 */
110 PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768@75 */
111 PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768@60 */
112 PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
113 PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
114 PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
115 PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
116 PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
117 PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
118 PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
119 PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
120 PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
121 PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
396 FFACTOR(0, "clk4m", "osc24m", 1, 6, 0),
397 FFACTOR(0, "clk2m", "osc24m", 1, 12, 0),
399 FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
400 FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
402 FFACTOR(0, "clk25m", "pll_mac", 1, 40, 0),
403 FFACTOR(0, "clk125m", "pll_mac", 1, 8, 0),
404 FFACTOR(0, "clk250m", "pll_mac", 1, 4, 0),
405 FFACTOR(0, "clk50m", "pll_mac", 1, 20, 0),
406 FFACTOR(0, "clk500m", "pll_mac", 1, 2, 0),
407 FFACTOR(0, "clk1000m", "pll_mac", 1, 1, 0),
408 FFACTOR(0, "clk334m", "pll_mac", 1, 3, 0),
409 FFACTOR(0, "clk167m", "pll_mac", 1, 6, 0),
411 FFACTOR(0, "clk54m_mm0", "pll_mm0", 1, 22, 0),
412 FFACTOR(0, "clk74m25", "pll_mm0", 1, 16, 0),
413 FFACTOR(0, "clk148m5", "pll_mm0", 1, 8, 0),
414 FFACTOR(0, "clk297m", "pll_mm0", 1, 4, 0),
415 FFACTOR(0, "clk594m", "pll_mm0", 1, 2, 0),
416 FFACTOR(0, "pll_mm0_1188m", "pll_mm0", 1, 1, 0),
417 FFACTOR(0, "clk396m", "pll_mm0", 1, 3, 0),
418 FFACTOR(0, "clk198m", "pll_mm0", 1, 6, 0),
419 FFACTOR(0, "clk99m", "pll_mm0", 1, 12, 0),
420 FFACTOR(0, "clk49m5", "pll_mm0", 1, 24, 0),
422 FFACTOR(0, "clk324m", "pll_mm1", 1, 4, 0),
423 FFACTOR(0, "clk648m", "pll_mm1", 1, 2, 0),
424 FFACTOR(0, "pll_mm1_1296m", "pll_mm1", 1, 1, 0),
425 FFACTOR(0, "clk216m", "pll_mm1", 1, 6, 0),
426 FFACTOR(0, "clk432m", "pll_mm1", 1, 3, 0),
427 FFACTOR(0, "clk108m", "pll_mm1", 1, 12, 0),
428 FFACTOR(0, "clk72m", "pll_mm1", 1, 18, 0),
429 FFACTOR(0, "clk27m", "pll_mm1", 1, 48, 0),
430 FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
432 FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
433 FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
435 FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
438 FFACTOR(0, "pll_audio_1800m", "pll_audio", 1, 1, 0),
439 FFACTOR(0, "clk32k768", "pll_audio", 1, 27000, 0),
440 FFACTOR(0, "clk16m384", "pll_audio", 1, 54, 0),
441 FFACTOR(0, "clk294m", "pll_audio", 1, 3, 0),
444 FFACTOR(0, "clk240m", "pll_hsic", 1, 4, 0),
445 FFACTOR(0, "clk480m", "pll_hsic", 1, 2, 0),
446 FFACTOR(0, "clk192m", "pll_hsic", 1, 5, 0),
447 FFACTOR(0, "clk_pll_24m", "pll_hsic", 1, 40, 0),
448 FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
456 DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
457 DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
461 MUX(0, "dbg_mux", dbg_wclk_p, TOP_CLK_MUX0, 12, 2),
462 MUX(0, "a72_mux", a72_coreclk_p, TOP_CLK_MUX0, 8, 3),
463 MUX(0, "cpu_peri_mux", cpu_periclk_p, TOP_CLK_MUX0, 4, 3),
464 MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
465 MUX(0, "sys_noc_aclk", sys_noc_alck_p, TOP_CLK_MUX1, 0, 3),
466 MUX(0, "sec_mux", sec_wclk_p, TOP_CLK_MUX2, 16, 3),
467 MUX(0, "sd1_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 12, 3),
468 MUX(0, "sd0_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 8, 3),
469 MUX(0, "emmc_mux", emmc_wclk_p, TOP_CLK_MUX2, 4, 3),
470 MUX(0, "nand_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 0, 3),
471 MUX(0, "usb_ref24m_mux", usb_ref24m_p, TOP_CLK_MUX9, 16, 1),
472 MUX(0, "clk32k", clk32_p, TOP_CLK_MUX9, 12, 1),
473 MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
474 MUX(0, "timer_mux", osc, TOP_CLK_MUX9, 4, 1),
475 MUX(0, "vde_mux", vde_aclk_p, TOP_CLK_MUX4, 0, 3),
476 MUX(0, "vce_mux", vce_aclk_p, TOP_CLK_MUX4, 4, 3),
477 MUX(0, "hde_mux", hde_aclk_p, TOP_CLK_MUX4, 8, 3),
478 MUX(0, "gpu_mux", gpu_aclk_p, TOP_CLK_MUX5, 0, 3),
479 MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
480 MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
481 MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
482 MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
483 MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
484 MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
485 MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
486 MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
487 MUX(0, "viu_m1_a_mux", viu_m1_aclk_p, TOP_CLK_MUX6, 4, 3),
488 MUX(0, "viu_w_mux", viu_clk_p, TOP_CLK_MUX6, 8, 3),
489 MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p, TOP_CLK_MUX6, 12, 3),
490 MUX(0, "ts_sys_mux", ts_sys_clk_p, TOP_CLK_MUX6, 16, 2),
494 …TE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
495 …TE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
496 …TE(CPU_PERI_GATE, "cpu_peri", "cpu_peri_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
497 …TE(A53_GATE, "a53_coreclk", "a53_mux", TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
498 …E(SD1_WCLK, "sd1_wclk", "sd1_mux", TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
499 …TE(SD0_WCLK, "sd0_wclk", "sd0_mux", TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
500 …TE(EMMC_WCLK, "emmc_wclk", "emmc_mux_div2", TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
501 …TE(EMMC_NAND_AXI, "emmc_nand_aclk", "sys_noc_aclk", TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
502 …TE(NAND_WCLK, "nand_wclk", "nand_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
503 …TE(EMMC_NAND_AHB, "emmc_nand_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
504 …GATE(0, "lsp1_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 31, 0, …
505 …TE(LSP1_148M5, "lsp1_148m5", "clk148m5", TOP_CLK_GATE2, 30, 0, 0),
506 …TE(LSP1_99M, "lsp1_99m", "clk99m", TOP_CLK_GATE2, 29, 0, 0),
507 …TE(LSP1_24M, "lsp1_24m", "osc24m", TOP_CLK_GATE2, 28, 0, 0),
508 …TE(LSP0_74M25, "lsp0_74m25", "clk74m25", TOP_CLK_GATE2, 25, 0, 0),
509 …GATE(0, "lsp0_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 24, 0, …
510 …TE(LSP0_32K, "lsp0_32k", "osc32k", TOP_CLK_GATE2, 23, 0, 0),
511 …TE(LSP0_148M5, "lsp0_148m5", "clk148m5", TOP_CLK_GATE2, 22, 0, 0),
512 …TE(LSP0_99M, "lsp0_99m", "clk99m", TOP_CLK_GATE2, 21, 0, 0),
513 …TE(LSP0_24M, "lsp0_24m", "osc24m", TOP_CLK_GATE2, 20, 0, 0),
514 …TE(AUDIO_99M, "audio_99m", "clk99m", TOP_CLK_GATE5, 27, 0, 0),
515 …TE(AUDIO_24M, "audio_24m", "osc24m", TOP_CLK_GATE5, 28, 0, 0),
516 …TE(AUDIO_16M384, "audio_16m384", "clk16m384", TOP_CLK_GATE5, 29, 0, 0),
517 …TE(AUDIO_32K, "audio_32k", "clk32k", TOP_CLK_GATE5, 30, 0, 0),
518 …TE(WDT_WCLK, "wdt_wclk", "wdt_mux", TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
519 …TE(TIMER_WCLK, "timer_wclk", "timer_mux", TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
520 …E(VDE_ACLK, "vde_aclk", "vde_mux", TOP_CLK_GATE3, 0, CLK_SET_RATE_PARENT, 0),
521 …E(VCE_ACLK, "vce_aclk", "vce_mux", TOP_CLK_GATE3, 4, CLK_SET_RATE_PARENT, 0),
522 …E(HDE_ACLK, "hde_aclk", "hde_mux", TOP_CLK_GATE3, 8, CLK_SET_RATE_PARENT, 0),
523 …E(GPU_ACLK, "gpu_aclk", "gpu_mux", TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
524 …E(SAPPU_ACLK, "sappu_aclk", "sappu_a_mux", TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
525 …E(SAPPU_WCLK, "sappu_wclk", "sappu_w_mux", TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
526 …E(VOU_ACLK, "vou_aclk", "vou_a_mux", TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
527 …E(VOU_MAIN_WCLK, "vou_main_wclk", "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
528 …E(VOU_AUX_WCLK, "vou_aux_wclk", "vou_aux_w_mux", TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
529 …E(VOU_PPU_WCLK, "vou_ppu_wclk", "vou_ppu_w_mux", TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
530 …E(MIPI_CFG_CLK, "mipi_cfg_clk", "osc24m", TOP_CLK_GATE4, 21, 0, 0),
531 …E(VGA_I2C_WCLK, "vga_i2c_wclk", "vga_i2c_mux", TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
532 …E(MIPI_REF_CLK, "mipi_ref_clk", "clk27m", TOP_CLK_GATE4, 24, 0, 0),
533 …E(HDMI_OSC_CEC, "hdmi_osc_cec", "clk2m", TOP_CLK_GATE4, 22, 0, 0),
534 …E(HDMI_OSC_CLK, "hdmi_osc_clk", "clk240m", TOP_CLK_GATE4, 25, 0, 0),
535 …E(HDMI_XCLK, "hdmi_xclk", "osc24m", TOP_CLK_GATE4, 26, 0, 0),
536 …E(VIU_M0_ACLK, "viu_m0_aclk", "viu_m0_a_mux", TOP_CLK_GATE4, 0, CLK_SET_RATE_PARENT, 0),
537 …E(VIU_M1_ACLK, "viu_m1_aclk", "viu_m1_a_mux", TOP_CLK_GATE4, 1, CLK_SET_RATE_PARENT, 0),
538 …E(VIU_WCLK, "viu_wclk", "viu_w_mux", TOP_CLK_GATE4, 2, CLK_SET_RATE_PARENT, 0),
539 …E(VIU_JPEG_WCLK, "viu_jpeg_wclk", "viu_jpeg_w_mux", TOP_CLK_GATE4, 3, CLK_SET_RATE_PARENT, 0),
540 …E(VIU_CFG_CLK, "viu_cfg_clk", "osc24m", TOP_CLK_GATE4, 6, 0, 0),
541 …E(TS_SYS_WCLK, "ts_sys_wclk", "ts_sys_mux", TOP_CLK_GATE5, 2, CLK_SET_RATE_PARENT, 0),
542 …E(TS_SYS_108M, "ts_sys_108m", "clk108m", TOP_CLK_GATE5, 3, 0, 0),
543 …E(USB20_HCLK, "usb20_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 12, 0, 0),
544 …E(USB20_PHY_CLK, "usb20_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0, 0),
545 …E(USB21_HCLK, "usb21_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 14, 0, 0),
546 …E(USB21_PHY_CLK, "usb21_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0, 0),
547 …E(GMAC_RMIICLK, "gmac_rmii_clk", "clk50m", TOP_CLK_GATE2, 3, 0, 0),
548 …E(GMAC_PCLK, "gmac_pclk", "clk198m", TOP_CLK_GATE2, 1, 0, 0),
549 …E(GMAC_ACLK, "gmac_aclk", "clk49m5", TOP_CLK_GATE2, 0, 0, 0),
550 …E(GMAC_RFCLK, "gmac_refclk", "clk25m", TOP_CLK_GATE2, 4, 0, 0),
551 …E(SD1_AHB, "sd1_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 12, 0, 0),
552 …E(SD0_AHB, "sd0_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 8, 0, 0),
553 …E(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m", TOP_CLK_GATE5, 31, 0, 0),
569 reg_base = of_iomap(np, 0); in top_clocks_init()
575 for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) { in top_clocks_init()
583 for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) { in top_clocks_init()
594 for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) { in top_clocks_init()
606 for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) { in top_clocks_init()
618 for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) { in top_clocks_init()
637 return 0; in top_clocks_init()
641 { .val = 0, .div = 1, },
653 { .val = 0, .div = 1, },
705 MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
706 MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
707 MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
708 MUX(0, "uart3_wclk_mux", lsp0_wclk_common_p, LSP0_UART3_CLK, 4, 1),
709 MUX(0, "uart1_wclk_mux", lsp0_wclk_common_p, LSP0_UART1_CLK, 4, 1),
710 MUX(0, "uart2_wclk_mux", lsp0_wclk_common_p, LSP0_UART2_CLK, 4, 1),
711 MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
712 MUX(0, "i2c4_wclk_mux", lsp0_wclk_common_p, LSP0_I2C4_CLK, 4, 1),
713 MUX(0, "i2c5_wclk_mux", lsp0_wclk_common_p, LSP0_I2C5_CLK, 4, 1),
714 MUX(0, "ssp0_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP0_CLK, 4, 1),
715 MUX(0, "ssp1_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP1_CLK, 4, 1),
716 MUX(0, "i2c3_wclk_mux", lsp0_wclk_common_p, LSP0_I2C3_CLK, 4, 1),
720 …TE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
721 …TE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
722 …TE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
723 …TE(LSP0_UART3_WCLK, "uart3_wclk", "uart3_wclk_mux", LSP0_UART3_CLK, 1, CLK_SET_RATE_PARENT, 0),
724 …TE(LSP0_UART1_WCLK, "uart1_wclk", "uart1_wclk_mux", LSP0_UART1_CLK, 1, CLK_SET_RATE_PARENT, 0),
725 …TE(LSP0_UART2_WCLK, "uart2_wclk", "uart2_wclk_mux", LSP0_UART2_CLK, 1, CLK_SET_RATE_PARENT, 0),
726 …TE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
727 …TE(LSP0_I2C4_WCLK, "i2c4_wclk", "i2c4_wclk_mux", LSP0_I2C4_CLK, 1, CLK_SET_RATE_PARENT, 0),
728 …TE(LSP0_I2C5_WCLK, "i2c5_wclk", "i2c5_wclk_mux", LSP0_I2C5_CLK, 1, CLK_SET_RATE_PARENT, 0),
729 …TE(LSP0_SSP0_WCLK, "ssp0_wclk", "ssp0_div", LSP0_SSP0_CLK, 1, CLK_SET_RATE_PARENT, 0),
730 …TE(LSP0_SSP1_WCLK, "ssp1_wclk", "ssp1_div", LSP0_SSP1_CLK, 1, CLK_SET_RATE_PARENT, 0),
731 …TE(LSP0_I2C3_WCLK, "i2c3_wclk", "i2c3_wclk_mux", LSP0_I2C3_CLK, 1, CLK_SET_RATE_PARENT, 0),
735 DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK, 12, 4, 0, common_even_div_table),
736 DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK, 12, 4, 0, common_even_div_table),
737 DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK, 12, 4, 0, common_even_div_table),
738 DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
739 DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
755 reg_base = of_iomap(np, 0); in lsp0_clocks_init()
761 for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) { in lsp0_clocks_init()
773 for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) { in lsp0_clocks_init()
785 for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) { in lsp0_clocks_init()
804 return 0; in lsp0_clocks_init()
819 MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
820 MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
821 MUX(0, "pwm_wclk_mux", lsp1_wclk_common_p, LSP1_PWM_CLK, 4, 1),
822 MUX(0, "i2c2_wclk_mux", lsp1_wclk_common_p, LSP1_I2C2_CLK, 4, 1),
823 MUX(0, "ssp2_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP2_CLK, 4, 2),
824 MUX(0, "ssp3_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP3_CLK, 4, 2),
825 MUX(0, "ssp4_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP4_CLK, 4, 2),
826 MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
830 DIV_T(0, "pwm_div", "pwm_wclk_mux", LSP1_PWM_CLK, 12, 4, CLK_SET_RATE_PARENT, common_div_table),
831 …DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_t…
832 …DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_t…
833 …DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_t…
837 …E(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
838 …E(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
839 …E(LSP1_PWM_WCLK, "lsp1_pwm_wclk", "pwm_div", LSP1_PWM_CLK, 1, CLK_SET_RATE_PARENT, 0),
840 GATE(LSP1_PWM_PCLK, "lsp1_pwm_pclk", "lsp1_pclk", LSP1_PWM_CLK, 0, 0, 0),
841 …E(LSP1_I2C2_WCLK, "lsp1_i2c2_wclk", "i2c2_wclk_mux", LSP1_I2C2_CLK, 1, CLK_SET_RATE_PARENT, 0),
842 …E(LSP1_SSP2_WCLK, "lsp1_ssp2_wclk", "ssp2_div", LSP1_SSP2_CLK, 1, CLK_SET_RATE_PARENT, 0),
843 …E(LSP1_SSP3_WCLK, "lsp1_ssp3_wclk", "ssp3_div", LSP1_SSP3_CLK, 1, CLK_SET_RATE_PARENT, 0),
844 …E(LSP1_SSP4_WCLK, "lsp1_ssp4_wclk", "ssp4_div", LSP1_SSP4_CLK, 1, CLK_SET_RATE_PARENT, 0),
845 …E(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
861 reg_base = of_iomap(np, 0); in lsp1_clocks_init()
867 for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) { in lsp1_clocks_init()
879 for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) { in lsp1_clocks_init()
891 for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) { in lsp1_clocks_init()
910 return 0; in lsp1_clocks_init()
924 MUX(I2S0_WCLK_MUX, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
925 MUX(I2S1_WCLK_MUX, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
926 MUX(I2S2_WCLK_MUX, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
927 MUX(I2S3_WCLK_MUX, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
928 MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
929 MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
930 MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
931 MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
935 AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
936 AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
937 AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
938 AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
939 AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
940 AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
944 DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
948 GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
949 GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
950 GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
951 GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
952 GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
953 GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
954 GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
955 GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
956 GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
957 …(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
958 …(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
959 GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
960 GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
976 reg_base = of_iomap(np, 0); in audio_clocks_init()
982 for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) { in audio_clocks_init()
994 for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) { in audio_clocks_init()
1006 for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) { in audio_clocks_init()
1018 for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) { in audio_clocks_init()
1037 return 0; in audio_clocks_init()