Lines Matching full:clk
7 #include <linux/clk-provider.h>
10 #include "clk.h"
18 static struct clk *topclk[ZX296702_TOPCLK_END];
19 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
20 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
196 static inline struct clk *zx_divtbl(const char *name, const char *parent, in zx_divtbl()
204 static inline struct clk *zx_div(const char *name, const char *parent, in zx_div()
211 static inline struct clk *zx_mux(const char *name, const char * const *parents, in zx_mux()
218 static inline struct clk *zx_gate(const char *name, const char *parent, in zx_gate()
227 struct clk **clk = topclk; in zx296702_top_clocks_init() local
233 clk[ZX296702_OSC] = in zx296702_top_clocks_init()
235 clk[ZX296702_PLL_A9] = in zx296702_top_clocks_init()
241 clk[ZX296702_PLL_A9_350M] = in zx296702_top_clocks_init()
244 clk[ZX296702_PLL_MAC_1000M] = in zx296702_top_clocks_init()
247 clk[ZX296702_PLL_MAC_333M] = in zx296702_top_clocks_init()
250 clk[ZX296702_PLL_MM0_1188M] = in zx296702_top_clocks_init()
253 clk[ZX296702_PLL_MM0_396M] = in zx296702_top_clocks_init()
256 clk[ZX296702_PLL_MM0_198M] = in zx296702_top_clocks_init()
259 clk[ZX296702_PLL_MM1_108M] = in zx296702_top_clocks_init()
262 clk[ZX296702_PLL_MM1_72M] = in zx296702_top_clocks_init()
265 clk[ZX296702_PLL_MM1_54M] = in zx296702_top_clocks_init()
268 clk[ZX296702_PLL_LSP_104M] = in zx296702_top_clocks_init()
271 clk[ZX296702_PLL_LSP_26M] = in zx296702_top_clocks_init()
274 clk[ZX296702_PLL_DDR_266M] = in zx296702_top_clocks_init()
277 clk[ZX296702_PLL_AUDIO_294M912] = in zx296702_top_clocks_init()
282 clk[ZX296702_MATRIX_ACLK] = in zx296702_top_clocks_init()
285 clk[ZX296702_MAIN_HCLK] = in zx296702_top_clocks_init()
288 clk[ZX296702_MAIN_PCLK] = in zx296702_top_clocks_init()
293 clk[ZX296702_CLK_500] = in zx296702_top_clocks_init()
296 clk[ZX296702_CLK_250] = in zx296702_top_clocks_init()
299 clk[ZX296702_CLK_125] = in zx296702_top_clocks_init()
301 clk[ZX296702_CLK_148M5] = in zx296702_top_clocks_init()
304 clk[ZX296702_CLK_74M25] = in zx296702_top_clocks_init()
307 clk[ZX296702_A9_WCLK] = in zx296702_top_clocks_init()
310 clk[ZX296702_A9_AS1_ACLK_MUX] = in zx296702_top_clocks_init()
313 clk[ZX296702_A9_TRACE_CLKIN_MUX] = in zx296702_top_clocks_init()
316 clk[ZX296702_A9_AS1_ACLK_DIV] = in zx296702_top_clocks_init()
321 clk[ZX296702_CLK_2] = in zx296702_top_clocks_init()
324 clk[ZX296702_CLK_27] = in zx296702_top_clocks_init()
327 clk[ZX296702_DECPPU_ACLK_MUX] = in zx296702_top_clocks_init()
330 clk[ZX296702_PPU_ACLK_MUX] = in zx296702_top_clocks_init()
333 clk[ZX296702_MALI400_ACLK_MUX] = in zx296702_top_clocks_init()
336 clk[ZX296702_VOU_ACLK_MUX] = in zx296702_top_clocks_init()
339 clk[ZX296702_VOU_MAIN_WCLK_MUX] = in zx296702_top_clocks_init()
342 clk[ZX296702_VOU_AUX_WCLK_MUX] = in zx296702_top_clocks_init()
345 clk[ZX296702_VOU_SCALER_WCLK_MUX] = in zx296702_top_clocks_init()
349 clk[ZX296702_R2D_ACLK_MUX] = in zx296702_top_clocks_init()
352 clk[ZX296702_R2D_WCLK_MUX] = in zx296702_top_clocks_init()
357 clk[ZX296702_CLK_50] = in zx296702_top_clocks_init()
360 clk[ZX296702_CLK_25] = in zx296702_top_clocks_init()
363 clk[ZX296702_CLK_12] = in zx296702_top_clocks_init()
366 clk[ZX296702_CLK_16M384] = in zx296702_top_clocks_init()
369 clk[ZX296702_CLK_32K768] = in zx296702_top_clocks_init()
372 clk[ZX296702_SEC_WCLK_DIV] = in zx296702_top_clocks_init()
375 clk[ZX296702_DDR_WCLK_MUX] = in zx296702_top_clocks_init()
378 clk[ZX296702_NAND_WCLK_MUX] = in zx296702_top_clocks_init()
381 clk[ZX296702_LSP_26_WCLK_MUX] = in zx296702_top_clocks_init()
386 clk[ZX296702_A9_AS0_ACLK] = in zx296702_top_clocks_init()
388 clk[ZX296702_A9_AS1_ACLK] = in zx296702_top_clocks_init()
390 clk[ZX296702_A9_TRACE_CLKIN] = in zx296702_top_clocks_init()
392 clk[ZX296702_DECPPU_AXI_M_ACLK] = in zx296702_top_clocks_init()
394 clk[ZX296702_DECPPU_AHB_S_HCLK] = in zx296702_top_clocks_init()
396 clk[ZX296702_PPU_AXI_M_ACLK] = in zx296702_top_clocks_init()
398 clk[ZX296702_PPU_AHB_S_HCLK] = in zx296702_top_clocks_init()
400 clk[ZX296702_VOU_AXI_M_ACLK] = in zx296702_top_clocks_init()
402 clk[ZX296702_VOU_APB_PCLK] = in zx296702_top_clocks_init()
404 clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] = in zx296702_top_clocks_init()
407 clk[ZX296702_VOU_AUX_CHANNEL_WCLK] = in zx296702_top_clocks_init()
410 clk[ZX296702_VOU_HDMI_OSCLK_CEC] = in zx296702_top_clocks_init()
412 clk[ZX296702_VOU_SCALER_WCLK] = in zx296702_top_clocks_init()
414 clk[ZX296702_MALI400_AXI_M_ACLK] = in zx296702_top_clocks_init()
416 clk[ZX296702_MALI400_APB_PCLK] = in zx296702_top_clocks_init()
418 clk[ZX296702_R2D_WCLK] = in zx296702_top_clocks_init()
420 clk[ZX296702_R2D_AXI_M_ACLK] = in zx296702_top_clocks_init()
422 clk[ZX296702_R2D_AHB_HCLK] = in zx296702_top_clocks_init()
424 clk[ZX296702_DDR3_AXI_S0_ACLK] = in zx296702_top_clocks_init()
426 clk[ZX296702_DDR3_APB_PCLK] = in zx296702_top_clocks_init()
428 clk[ZX296702_DDR3_WCLK] = in zx296702_top_clocks_init()
430 clk[ZX296702_USB20_0_AHB_HCLK] = in zx296702_top_clocks_init()
432 clk[ZX296702_USB20_0_EXTREFCLK] = in zx296702_top_clocks_init()
434 clk[ZX296702_USB20_1_AHB_HCLK] = in zx296702_top_clocks_init()
436 clk[ZX296702_USB20_1_EXTREFCLK] = in zx296702_top_clocks_init()
438 clk[ZX296702_USB20_2_AHB_HCLK] = in zx296702_top_clocks_init()
440 clk[ZX296702_USB20_2_EXTREFCLK] = in zx296702_top_clocks_init()
442 clk[ZX296702_GMAC_AXI_M_ACLK] = in zx296702_top_clocks_init()
444 clk[ZX296702_GMAC_APB_PCLK] = in zx296702_top_clocks_init()
446 clk[ZX296702_GMAC_125_CLKIN] = in zx296702_top_clocks_init()
448 clk[ZX296702_GMAC_RMII_CLKIN] = in zx296702_top_clocks_init()
450 clk[ZX296702_GMAC_25M_CLK] = in zx296702_top_clocks_init()
452 clk[ZX296702_NANDFLASH_AHB_HCLK] = in zx296702_top_clocks_init()
454 clk[ZX296702_NANDFLASH_WCLK] = in zx296702_top_clocks_init()
456 clk[ZX296702_LSP0_APB_PCLK] = in zx296702_top_clocks_init()
458 clk[ZX296702_LSP0_AHB_HCLK] = in zx296702_top_clocks_init()
460 clk[ZX296702_LSP0_26M_WCLK] = in zx296702_top_clocks_init()
462 clk[ZX296702_LSP0_104M_WCLK] = in zx296702_top_clocks_init()
464 clk[ZX296702_LSP0_16M384_WCLK] = in zx296702_top_clocks_init()
466 clk[ZX296702_LSP1_APB_PCLK] = in zx296702_top_clocks_init()
469 * UART does not work after parent clk is disabled/enabled */ in zx296702_top_clocks_init()
470 clk[ZX296702_LSP1_26M_WCLK] = in zx296702_top_clocks_init()
472 clk[ZX296702_LSP1_104M_WCLK] = in zx296702_top_clocks_init()
474 clk[ZX296702_LSP1_32K_CLK] = in zx296702_top_clocks_init()
476 clk[ZX296702_AON_HCLK] = in zx296702_top_clocks_init()
478 clk[ZX296702_SYS_CTRL_PCLK] = in zx296702_top_clocks_init()
480 clk[ZX296702_DMA_PCLK] = in zx296702_top_clocks_init()
482 clk[ZX296702_DMA_ACLK] = in zx296702_top_clocks_init()
484 clk[ZX296702_SEC_HCLK] = in zx296702_top_clocks_init()
486 clk[ZX296702_AES_WCLK] = in zx296702_top_clocks_init()
488 clk[ZX296702_DES_WCLK] = in zx296702_top_clocks_init()
490 clk[ZX296702_IRAM_ACLK] = in zx296702_top_clocks_init()
492 clk[ZX296702_IROM_ACLK] = in zx296702_top_clocks_init()
494 clk[ZX296702_BOOT_CTRL_HCLK] = in zx296702_top_clocks_init()
496 clk[ZX296702_EFUSE_CLK_30] = in zx296702_top_clocks_init()
500 clk[ZX296702_VOU_MAIN_CHANNEL_DIV] = in zx296702_top_clocks_init()
503 clk[ZX296702_VOU_AUX_CHANNEL_DIV] = in zx296702_top_clocks_init()
506 clk[ZX296702_VOU_TV_ENC_HD_DIV] = in zx296702_top_clocks_init()
509 clk[ZX296702_VOU_TV_ENC_SD_DIV] = in zx296702_top_clocks_init()
512 clk[ZX296702_VL0_MUX] = in zx296702_top_clocks_init()
515 clk[ZX296702_VL1_MUX] = in zx296702_top_clocks_init()
518 clk[ZX296702_VL2_MUX] = in zx296702_top_clocks_init()
521 clk[ZX296702_GL0_MUX] = in zx296702_top_clocks_init()
524 clk[ZX296702_GL1_MUX] = in zx296702_top_clocks_init()
527 clk[ZX296702_GL2_MUX] = in zx296702_top_clocks_init()
530 clk[ZX296702_WB_MUX] = in zx296702_top_clocks_init()
533 clk[ZX296702_HDMI_MUX] = in zx296702_top_clocks_init()
536 clk[ZX296702_VOU_TV_ENC_HD_MUX] = in zx296702_top_clocks_init()
539 clk[ZX296702_VOU_TV_ENC_SD_MUX] = in zx296702_top_clocks_init()
542 clk[ZX296702_VL0_CLK] = in zx296702_top_clocks_init()
544 clk[ZX296702_VL1_CLK] = in zx296702_top_clocks_init()
546 clk[ZX296702_VL2_CLK] = in zx296702_top_clocks_init()
548 clk[ZX296702_GL0_CLK] = in zx296702_top_clocks_init()
550 clk[ZX296702_GL1_CLK] = in zx296702_top_clocks_init()
552 clk[ZX296702_GL2_CLK] = in zx296702_top_clocks_init()
554 clk[ZX296702_WB_CLK] = in zx296702_top_clocks_init()
556 clk[ZX296702_CL_CLK] = in zx296702_top_clocks_init()
558 clk[ZX296702_MAIN_MIX_CLK] = in zx296702_top_clocks_init()
561 clk[ZX296702_AUX_MIX_CLK] = in zx296702_top_clocks_init()
564 clk[ZX296702_HDMI_CLK] = in zx296702_top_clocks_init()
566 clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] = in zx296702_top_clocks_init()
569 clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] = in zx296702_top_clocks_init()
574 clk[ZX296702_A9_PERIPHCLK] = in zx296702_top_clocks_init()
579 if (IS_ERR(clk[i])) { in zx296702_top_clocks_init()
580 pr_err("zx296702 clk %d: register failed with %ld\n", in zx296702_top_clocks_init()
581 i, PTR_ERR(clk[i])); in zx296702_top_clocks_init()
590 CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
595 struct clk **clk = lsp0clk; in zx296702_lsp0_clocks_init() local
602 clk[ZX296702_SDMMC1_WCLK_MUX] = in zx296702_lsp0_clocks_init()
605 clk[ZX296702_SDMMC1_WCLK_DIV] = in zx296702_lsp0_clocks_init()
607 clk[ZX296702_SDMMC1_WCLK] = in zx296702_lsp0_clocks_init()
609 clk[ZX296702_SDMMC1_PCLK] = in zx296702_lsp0_clocks_init()
612 clk[ZX296702_GPIO_CLK] = in zx296702_lsp0_clocks_init()
616 clk[ZX296702_SPDIF0_WCLK_MUX] = in zx296702_lsp0_clocks_init()
619 clk[ZX296702_SPDIF0_WCLK] = in zx296702_lsp0_clocks_init()
621 clk[ZX296702_SPDIF0_PCLK] = in zx296702_lsp0_clocks_init()
624 clk[ZX296702_SPDIF0_DIV] = in zx296702_lsp0_clocks_init()
629 clk[ZX296702_I2S0_WCLK_MUX] = in zx296702_lsp0_clocks_init()
632 clk[ZX296702_I2S0_WCLK] = in zx296702_lsp0_clocks_init()
634 clk[ZX296702_I2S0_PCLK] = in zx296702_lsp0_clocks_init()
637 clk[ZX296702_I2S0_DIV] = in zx296702_lsp0_clocks_init()
640 clk[ZX296702_I2S1_WCLK_MUX] = in zx296702_lsp0_clocks_init()
643 clk[ZX296702_I2S1_WCLK] = in zx296702_lsp0_clocks_init()
645 clk[ZX296702_I2S1_PCLK] = in zx296702_lsp0_clocks_init()
648 clk[ZX296702_I2S1_DIV] = in zx296702_lsp0_clocks_init()
651 clk[ZX296702_I2S2_WCLK_MUX] = in zx296702_lsp0_clocks_init()
654 clk[ZX296702_I2S2_WCLK] = in zx296702_lsp0_clocks_init()
656 clk[ZX296702_I2S2_PCLK] = in zx296702_lsp0_clocks_init()
659 clk[ZX296702_I2S2_DIV] = in zx296702_lsp0_clocks_init()
663 if (IS_ERR(clk[i])) { in zx296702_lsp0_clocks_init()
664 pr_err("zx296702 clk %d: register failed with %ld\n", in zx296702_lsp0_clocks_init()
665 i, PTR_ERR(clk[i])); in zx296702_lsp0_clocks_init()
674 CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
679 struct clk **clk = lsp1clk; in zx296702_lsp1_clocks_init() local
686 clk[ZX296702_UART0_WCLK_MUX] = in zx296702_lsp1_clocks_init()
690 * UART does not work after parent clk is disabled/enabled */ in zx296702_lsp1_clocks_init()
691 clk[ZX296702_UART0_WCLK] = in zx296702_lsp1_clocks_init()
693 clk[ZX296702_UART0_PCLK] = in zx296702_lsp1_clocks_init()
697 clk[ZX296702_UART1_WCLK_MUX] = in zx296702_lsp1_clocks_init()
700 clk[ZX296702_UART1_WCLK] = in zx296702_lsp1_clocks_init()
702 clk[ZX296702_UART1_PCLK] = in zx296702_lsp1_clocks_init()
706 clk[ZX296702_SDMMC0_WCLK_MUX] = in zx296702_lsp1_clocks_init()
709 clk[ZX296702_SDMMC0_WCLK_DIV] = in zx296702_lsp1_clocks_init()
711 clk[ZX296702_SDMMC0_WCLK] = in zx296702_lsp1_clocks_init()
713 clk[ZX296702_SDMMC0_PCLK] = in zx296702_lsp1_clocks_init()
716 clk[ZX296702_SPDIF1_WCLK_MUX] = in zx296702_lsp1_clocks_init()
719 clk[ZX296702_SPDIF1_WCLK] = in zx296702_lsp1_clocks_init()
721 clk[ZX296702_SPDIF1_PCLK] = in zx296702_lsp1_clocks_init()
724 clk[ZX296702_SPDIF1_DIV] = in zx296702_lsp1_clocks_init()
729 if (IS_ERR(clk[i])) { in zx296702_lsp1_clocks_init()
730 pr_err("zx296702 clk %d: register failed with %ld\n", in zx296702_lsp1_clocks_init()
731 i, PTR_ERR(clk[i])); in zx296702_lsp1_clocks_init()
740 CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",