Lines Matching refs:PLL_DDIV_WIDTH

14 #define PLL_DDIV_WIDTH		3  macro
406 		 PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
407 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
409 		 PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
410 		 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
412 		 PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
413 		 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
415 		 PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
416 		 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
418 		 PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,
419 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),