clk/x86/clk-lgm.c

1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
10 #include <dt-bindings/clock/intel,lgm-clk.h>
11 #include "clk-cgu.h"
29 #define G_LEDC0_SHIFT		1
60 #define G_PCIE10_SHIFT		1
115 #define CLK_NR_CLKS		(LGM_GCLK_USB2 + 1)
119  * It's more efficient to provide an explicit table due to non-linear
123 	{ .val = 0, .div = 1 },
124 	{ .val = 1, .div = 2 },
144 	{ .val = 1, .div = 12 },
194 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
196 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
198 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
200 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
202 		PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
205 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
209 		1, 0, 0, pll_div),
212 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
216 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
219 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
229 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
232 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
234 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
236 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
238 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
240 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
242 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
245 			 0, 0, 0, 0, 1, 4),
247 			 0, 0, 0, 0, 1, 4),
249 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
250 	LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
251 		1, 1, CLK_MUX_ROUND_CLOSEST, 0),
259 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
262 			 0, 0, 0, 0, 2, 1),
264 			 CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
284 	LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
407 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
410 		 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
413 		 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
416 		 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
419 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
425 	struct device *dev = &pdev->dev;  in lgm_cgu_probe()
426 	struct device_node *np = dev->of_node;  in lgm_cgu_probe()
432 		return -ENOMEM;  in lgm_cgu_probe()
434 	ctx->clk_data.num = CLK_NR_CLKS;  in lgm_cgu_probe()
436 	ctx->membase = devm_platform_ioremap_resource(pdev, 0);  in lgm_cgu_probe()
437 	if (IS_ERR(ctx->membase))  in lgm_cgu_probe()
438 		return PTR_ERR(ctx->membase);  in lgm_cgu_probe()
440 	ctx->np = np;  in lgm_cgu_probe()
441 	ctx->dev = dev;  in lgm_cgu_probe()
442 	spin_lock_init(&ctx->lock);  in lgm_cgu_probe()
460 					   &ctx->clk_data);  in lgm_cgu_probe()
464 	{ .compatible = "intel,cgu-lgm" },
471 		   .name = "cgu-lgm",