clk/ti/clk-54xx.c

48 	{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
67 	{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
80 	{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
93 	{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
106 	{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
118 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
128 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
133 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
139 	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
141 	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
142 	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
143 	{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
144 	{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
145 	{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
146 	{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
147 	{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
148 	{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
199 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
204 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
209 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
214 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
219 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
224 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
269 	{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
270 	{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
271 	{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
272 	{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
273 	{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
274 	{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
372 	{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
379 	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
390 	"l3init_cm:clk:0008:24",
400 	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
406 	"l3init_cm:clk:0010:24",
415 	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
431 	"l3init_cm:clk:0038:24",
462 	{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
512 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
520 	{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
550 	DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
564 	DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
566 	DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
568 	DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
572 	DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
574 	DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
576 	DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
577 	DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
578 	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
579 	DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
580 	DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
581 	DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
582 	DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
583 	DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
584 	DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
585 	DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
586 	DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
600 	DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),