6  * J Keerthy <j-keerthy@ti.com>
19 #include <linux/clk-provider.h>
49 	ad = clk->dpll_data;  in dra7_apll_enable()
51 		return -EINVAL;  in dra7_apll_enable()
53 	clk_name = clk_hw_get_name(&clk->hw);  in dra7_apll_enable()
55 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
58 	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
60 	if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
63 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_enable()
64 	v &= ~ad->enable_mask;  in dra7_apll_enable()
65 	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);  in dra7_apll_enable()
66 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_enable()
68 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
71 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
72 		if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
83 		r = -EBUSY;  in dra7_apll_enable()
98 	ad = clk->dpll_data;  in dra7_apll_disable()
100 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_disable()
102 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_disable()
103 	v &= ~ad->enable_mask;  in dra7_apll_disable()
104 	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);  in dra7_apll_disable()
105 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_disable()
114 	ad = clk->dpll_data;  in dra7_apll_is_enabled()
116 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_is_enabled()
117 	v &= ad->enable_mask;  in dra7_apll_is_enabled()
119 	v >>= __ffs(ad->enable_mask);  in dra7_apll_is_enabled()
141 	struct dpll_data *ad = clk_hw->dpll_data;  in omap_clk_register_apll()
143 	const struct clk_init_data *init = clk_hw->hw.init;  in omap_clk_register_apll()  local
147 		pr_debug("clk-ref for %pOFn not ready, retry\n",  in omap_clk_register_apll()
155 	ad->clk_ref = __clk_get_hw(clk);  in omap_clk_register_apll()
159 		pr_debug("clk-bypass for %pOFn not ready, retry\n",  in omap_clk_register_apll()
167 	ad->clk_bypass = __clk_get_hw(clk);  in omap_clk_register_apll()
169 	clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);  in omap_clk_register_apll()
172 		kfree(init->parent_names);  in omap_clk_register_apll()
173 		kfree(init);  in omap_clk_register_apll()
178 	kfree(clk_hw->dpll_data);  in omap_clk_register_apll()
179 	kfree(init->parent_names);  in omap_clk_register_apll()
180 	kfree(init);  in omap_clk_register_apll()
188 	struct clk_init_data *init = NULL;  in of_dra7_apll_setup()  local
194 	init = kzalloc(sizeof(*init), GFP_KERNEL);  in of_dra7_apll_setup()
195 	if (!ad || !clk_hw || !init)  in of_dra7_apll_setup()
198 	clk_hw->dpll_data = ad;  in of_dra7_apll_setup()
199 	clk_hw->hw.init = init;  in of_dra7_apll_setup()
201 	init->name = node->name;  in of_dra7_apll_setup()
202 	init->ops = &apll_ck_ops;  in of_dra7_apll_setup()
204 	init->num_parents = of_clk_get_parent_count(node);  in of_dra7_apll_setup()
205 	if (init->num_parents < 1) {  in of_dra7_apll_setup()
210 	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);  in of_dra7_apll_setup()
214 	of_clk_parent_fill(node, parent_names, init->num_parents);  in of_dra7_apll_setup()
216 	init->parent_names = parent_names;  in of_dra7_apll_setup()
218 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_dra7_apll_setup()
219 	ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);  in of_dra7_apll_setup()
224 	ad->idlest_mask = 0x1;  in of_dra7_apll_setup()
225 	ad->enable_mask = 0x3;  in of_dra7_apll_setup()
227 	omap_clk_register_apll(&clk_hw->hw, node);  in of_dra7_apll_setup()
234 	kfree(init);  in of_dra7_apll_setup()
236 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
244 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_is_enabled()
247 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_is_enabled()
248 	v &= ad->enable_mask;  in omap2_apll_is_enabled()
250 	v >>= __ffs(ad->enable_mask);  in omap2_apll_is_enabled()
261 		return clk->fixed_rate;  in omap2_apll_recalc()
269 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_enable()
273 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_enable()
274 	v &= ~ad->enable_mask;  in omap2_apll_enable()
275 	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);  in omap2_apll_enable()
276 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_enable()
279 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in omap2_apll_enable()
280 		if (v & ad->idlest_mask)  in omap2_apll_enable()
290 			clk_hw_get_name(&clk->hw));  in omap2_apll_enable()
291 		return -EBUSY;  in omap2_apll_enable()
300 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_disable()
303 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_disable()
304 	v &= ~ad->enable_mask;  in omap2_apll_disable()
305 	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);  in omap2_apll_disable()
306 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_disable()
318 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_set_autoidle()
321 	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);  in omap2_apll_set_autoidle()
322 	v &= ~ad->autoidle_mask;  in omap2_apll_set_autoidle()
323 	v |= val << __ffs(ad->autoidle_mask);  in omap2_apll_set_autoidle()
324 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_set_autoidle()
349 	struct clk_init_data *init = NULL;  in of_omap2_apll_setup()  local
357 	init = kzalloc(sizeof(*init), GFP_KERNEL);  in of_omap2_apll_setup()
359 	if (!ad || !clk_hw || !init)  in of_omap2_apll_setup()
362 	clk_hw->dpll_data = ad;  in of_omap2_apll_setup()
363 	clk_hw->hw.init = init;  in of_omap2_apll_setup()
364 	init->ops = &omap2_apll_ops;  in of_omap2_apll_setup()
365 	init->name = node->name;  in of_omap2_apll_setup()
366 	clk_hw->ops = &omap2_apll_hwops;  in of_omap2_apll_setup()
368 	init->num_parents = of_clk_get_parent_count(node);  in of_omap2_apll_setup()
369 	if (init->num_parents != 1) {  in of_omap2_apll_setup()
375 	init->parent_names = &parent_name;  in of_omap2_apll_setup()
377 	if (of_property_read_u32(node, "ti,clock-frequency", &val)) {  in of_omap2_apll_setup()
378 		pr_err("%pOFn missing clock-frequency\n", node);  in of_omap2_apll_setup()
381 	clk_hw->fixed_rate = val;  in of_omap2_apll_setup()
383 	if (of_property_read_u32(node, "ti,bit-shift", &val)) {  in of_omap2_apll_setup()
384 		pr_err("%pOFn missing bit-shift\n", node);  in of_omap2_apll_setup()
388 	clk_hw->enable_bit = val;  in of_omap2_apll_setup()
389 	ad->enable_mask = 0x3 << val;  in of_omap2_apll_setup()
390 	ad->autoidle_mask = 0x3 << val;  in of_omap2_apll_setup()
392 	if (of_property_read_u32(node, "ti,idlest-shift", &val)) {  in of_omap2_apll_setup()
393 		pr_err("%pOFn missing idlest-shift\n", node);  in of_omap2_apll_setup()
397 	ad->idlest_mask = 1 << val;  in of_omap2_apll_setup()
399 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_omap2_apll_setup()
400 	ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);  in of_omap2_apll_setup()
401 	ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);  in of_omap2_apll_setup()
406 	clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);  in of_omap2_apll_setup()
409 		kfree(init);  in of_omap2_apll_setup()
415 	kfree(init);  in of_omap2_apll_setup()
417 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",