1123 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)  in tegra210_pllx_set_defaults()  argument
1128 	pllx->params->defaults_set = true;  in tegra210_pllx_set_defaults()
1131 	pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);  in tegra210_pllx_set_defaults()
1137 	if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {  in tegra210_pllx_set_defaults()
1143 		pllx_check_defaults(pllx);  in tegra210_pllx_set_defaults()
1145 		if (!pllx->params->defaults_set)  in tegra210_pllx_set_defaults()
1148 		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_set_defaults()
1151 		val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1154 		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1162 			pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1166 			pllx->params->ext_misc_reg[1]);  in tegra210_pllx_set_defaults()
1169 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_set_defaults()
1173 			pllx->params->ext_misc_reg[3]);  in tegra210_pllx_set_defaults()
1177 			pllx->params->ext_misc_reg[4]);  in tegra210_pllx_set_defaults()
1179 			pllx->params->ext_misc_reg[5]);  in tegra210_pllx_set_defaults()
1379 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,  in tegra210_pllx_dyn_ramp()  argument
1384 	ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)  in tegra210_pllx_dyn_ramp()
1387 	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1390 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1393 	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1395 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1398 	tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],  in tegra210_pllx_dyn_ramp()
1401 	base = readl_relaxed(clk_base + pllx->params->base_reg) &  in tegra210_pllx_dyn_ramp()
1402 		(~divn_mask_shifted(pllx));  in tegra210_pllx_dyn_ramp()
1403 	base |= cfg->n << pllx->params->div_nmp->divn_shift;  in tegra210_pllx_dyn_ramp()
1404 	writel_relaxed(base, clk_base + pllx->params->base_reg);  in tegra210_pllx_dyn_ramp()
1408 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1412 		 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,  in tegra210_pllx_dyn_ramp()
1414 		 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);  in tegra210_pllx_dyn_ramp()