1308 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)  in tegra210_pllu_set_defaults()  argument
1310 	u32 val = readl_relaxed(clk_base + pllu->base_reg);  in tegra210_pllu_set_defaults()
1312 	pllu->defaults_set = true;  in tegra210_pllu_set_defaults()
1320 		pllu_check_defaults(pllu, false);  in tegra210_pllu_set_defaults()
1321 		if (!pllu->defaults_set)  in tegra210_pllu_set_defaults()
1325 		val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1328 		writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1330 		val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
1333 		writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
1341 			clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1343 			clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
2844 	struct tegra_clk_pll pllu;  in tegra210_enable_pllu()  local
2859 	pllu.params = &pll_u_vco_params;  in tegra210_enable_pllu()
2860 	reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);  in tegra210_enable_pllu()
2861 	reg &= ~BIT(pllu.params->iddq_bit_idx);  in tegra210_enable_pllu()
2862 	writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);  in tegra210_enable_pllu()
2881 	ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);  in tegra210_enable_pllu()