clk/tegra/clk-tegra210.c

2510 	{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2511 	{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2512 	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2513 	{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
2514 	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
2515 	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
2516 	{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2517 	{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2518 	{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2519 	{ .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2520 	{ .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2521 	{ .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2522 	{ .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2523 	{ .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2524 	{ .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2525 	{ .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2526 	{ .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2527 	{ .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2528 	{ .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2529 	{ .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2530 	{ .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2531 	{ .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2532 	{ .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2533 	{ .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2534 	{ .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2535 	{ .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2536 	{ .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2537 	{ .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2538 	{ .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2539 	{ .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2540 	{ .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2541 	{ .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2542 	{ .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2543 	{ .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2544 	{ .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2545 	{ .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2546 	{ .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2547 	{ .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2548 	{ .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2549 	{ .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2550 	{ .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2551 	{ .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2552 	{ .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2553 	{ .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2554 	{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2555 	{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2556 	{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2557 	{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
2558 	{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
2559 	{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
2560 	{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2561 	{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2562 	{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2563 	{ .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2564 	{ .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2565 	{ .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2568 	{ .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2569 	{ .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2570 	{ .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2571 	{ .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2572 	{ .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },