Lines Matching +full:0 +full:x702d0000
33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
43 #define PLLC_OUT 0x84
44 #define PLLC_MISC0 0x88
45 #define PLLC_MISC1 0x8c
46 #define PLLC_MISC2 0x5d0
47 #define PLLC_MISC3 0x5d4
49 #define PLLC2_BASE 0x4e8
50 #define PLLC2_MISC0 0x4ec
51 #define PLLC2_MISC1 0x4f0
52 #define PLLC2_MISC2 0x4f4
53 #define PLLC2_MISC3 0x4f8
55 #define PLLC3_BASE 0x4fc
56 #define PLLC3_MISC0 0x500
57 #define PLLC3_MISC1 0x504
58 #define PLLC3_MISC2 0x508
59 #define PLLC3_MISC3 0x50c
61 #define PLLM_BASE 0x90
62 #define PLLM_MISC1 0x98
63 #define PLLM_MISC2 0x9c
64 #define PLLP_BASE 0xa0
65 #define PLLP_MISC0 0xac
66 #define PLLP_MISC1 0x680
67 #define PLLA_BASE 0xb0
68 #define PLLA_MISC0 0xbc
69 #define PLLA_MISC1 0xb8
70 #define PLLA_MISC2 0x5d8
71 #define PLLD_BASE 0xd0
72 #define PLLD_MISC0 0xdc
73 #define PLLD_MISC1 0xd8
74 #define PLLU_BASE 0xc0
75 #define PLLU_OUTA 0xc4
76 #define PLLU_MISC0 0xcc
77 #define PLLU_MISC1 0xc8
78 #define PLLX_BASE 0xe0
79 #define PLLX_MISC0 0xe4
80 #define PLLX_MISC1 0x510
81 #define PLLX_MISC2 0x514
82 #define PLLX_MISC3 0x518
83 #define PLLX_MISC4 0x5f0
84 #define PLLX_MISC5 0x5f4
85 #define PLLE_BASE 0xe8
86 #define PLLE_MISC0 0xec
87 #define PLLD2_BASE 0x4b8
88 #define PLLD2_MISC0 0x4bc
89 #define PLLD2_MISC1 0x570
90 #define PLLD2_MISC2 0x574
91 #define PLLD2_MISC3 0x578
92 #define PLLE_AUX 0x48c
93 #define PLLRE_BASE 0x4c4
94 #define PLLRE_MISC0 0x4c8
95 #define PLLRE_OUT1 0x4cc
96 #define PLLDP_BASE 0x590
97 #define PLLDP_MISC 0x594
99 #define PLLC4_BASE 0x5a4
100 #define PLLC4_MISC0 0x5a8
101 #define PLLC4_OUT 0x5e4
102 #define PLLMB_BASE 0x5e8
103 #define PLLMB_MISC1 0x5ec
104 #define PLLA1_BASE 0x6a4
105 #define PLLA1_MISC0 0x6a8
106 #define PLLA1_MISC1 0x6ac
107 #define PLLA1_MISC2 0x6b0
108 #define PLLA1_MISC3 0x6b4
141 #define PLLA_SDM_DIN_MASK 0xffff
147 #define PLLD2_SSC_EN_MASK 0
149 #define PLLDP_SS_CFG 0x598
152 #define PLLDP_SS_CTRL1 0x59c
153 #define PLLDP_SS_CTRL2 0x5a0
155 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
156 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
158 #define UTMIP_PLL_CFG2 0x488
159 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
160 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
170 #define UTMIP_PLL_CFG1 0x484
171 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
172 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
179 #define SATA_PLL_CFG0 0x490
180 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
190 #define XUSBIO_PLL_CFG0 0x51c
191 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
197 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
209 #define PLLU_HW_PWRDN_CFG0 0x530
215 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
217 #define XUSB_PLL_CFG0 0x534
218 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
219 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
221 #define SPARE_REG0 0x55c
223 #define CLK_M_DIVISOR_MASK 0x3
225 #define CLK_MASK_ARM 0x44
226 #define MISC_CLK_ENB 0x48
228 #define RST_DFLL_DVCO 0x2f4
229 #define DVFS_DFLL_RESET_SHIFT 0
231 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284
232 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288
235 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
236 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
237 #define CPU_SOFTRST_CTRL 0x380
239 #define LVL2_CLK_GATE_OVRA 0xf8
240 #define LVL2_CLK_GATE_OVRC 0x3a0
241 #define LVL2_CLK_GATE_OVRD 0x3a4
242 #define LVL2_CLK_GATE_OVRE 0x554
245 #define TEGRA210_I2S_BASE 0x1000
246 #define TEGRA210_I2S_SIZE 0x100
248 #define TEGRA210_I2S_CG 0x88
249 #define TEGRA210_I2S_CTRL 0xa0
252 #define DC_CMD_DISPLAY_COMMAND 0xc8
253 #define DC_COM_DSC_TOP_CTL 0xcf8
256 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
259 #define TEGRA210_AHUB_BASE 0x702d0000
260 #define TEGRA210_DISPA_BASE 0x54200000
261 #define TEGRA210_VIC_BASE 0x54340000
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
272 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
273 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
276 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
279 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
327 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
328 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
329 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
330 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
331 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
332 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
333 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
334 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
346 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
347 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
348 #define PLLA_MISC2_DEFAULT_VALUE 0x0
349 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
360 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
361 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
362 #define PLLD_MISC1_DEFAULT_VALUE 0x20
363 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
370 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
377 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
378 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
379 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
380 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
382 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
383 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
384 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
385 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
387 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
388 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
389 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
390 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
392 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
400 #define PLLRE_BASE_DEFAULT_VALUE 0x0
401 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
403 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
404 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
410 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
411 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
414 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
416 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
418 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
419 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
420 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
421 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
423 #define PLLX_MISC3_IDDQ (0x1 << 3)
426 #define PLLX_MISC0_WRITE_MASK 0x10c40000
427 #define PLLX_MISC1_DEFAULT_VALUE 0x20
428 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
429 #define PLLX_MISC2_DEFAULT_VALUE 0x0
430 #define PLLX_MISC2_WRITE_MASK 0xffffff11
432 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
433 #define PLLX_MISC4_DEFAULT_VALUE 0x0
434 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
435 #define PLLX_MISC5_DEFAULT_VALUE 0x0
436 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
438 #define PLLX_HW_CTRL_CFG 0x548
439 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
448 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
449 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
464 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
465 #define PLLP_MISC1_DEFAULT_VALUE 0x0
467 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
468 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
484 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
486 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
487 #define PLLU_MISC1_DEFAULT_VALUE 0x0
489 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
490 #define PLLU_MISC1_WRITE_MASK 0x00000007
592 unsigned long flags = 0; in tegra210_venc_mbist_war()
641 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), in tegra210_vic_mbist_war()
667 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) { in tegra210_ape_mbist_war()
673 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG); in tegra210_ape_mbist_war()
696 pr_warn("boot misc%d 0x%x: expected 0x%x\n", in _pll_misc_chk_default()
698 pr_warn(" (comparison mask = 0x%x)\n", mask); in _pll_misc_chk_default()
713 _pll_misc_chk_default(clk_base, params, 0, default_val, in pllcx_check_defaults()
745 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
801 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
809 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
812 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
822 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
835 u32 mask = 0xffff; in tegra210_plld_set_defaults()
854 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
862 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
865 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
871 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
875 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
906 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, in plldss_defaults()
943 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
946 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
960 plldss->params->ext_misc_reg[0]); in plldss_defaults()
966 plldss->params->ext_misc_reg[0]); in plldss_defaults()
998 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); in tegra210_pllc4_set_defaults()
1019 pr_warn("pllre boot base 0x%x : expected 0x%x\n", in tegra210_pllre_set_defaults()
1021 pr_warn("(comparison mask = 0x%x)\n", in tegra210_pllre_set_defaults()
1029 _pll_misc_chk_default(clk_base, pllre->params, 0, val, in tegra210_pllre_set_defaults()
1033 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1040 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1054 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1074 *step_a = 0x2B; in pllx_get_dyn_steps()
1075 *step_b = 0x0B; in pllx_get_dyn_steps()
1078 *step_a = 0x12; in pllx_get_dyn_steps()
1079 *step_b = 0x08; in pllx_get_dyn_steps()
1082 *step_a = 0x04; in pllx_get_dyn_steps()
1083 *step_b = 0x05; in pllx_get_dyn_steps()
1098 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, in pllx_check_defaults()
1151 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1154 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1162 pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1198 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, in tegra210_pllmb_set_defaults()
1204 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1207 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1215 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1234 _pll_misc_chk_default(clk_base, pll->params, 0, val, in pllp_check_defaults()
1262 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1266 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1274 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1298 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); in pllu_check_defaults()
1299 _pll_misc_chk_default(clk_base, params, 0, val, in pllu_check_defaults()
1325 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1328 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1341 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1366 u32 val = 0; in tegra210_wait_for_mask()
1368 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { in tegra210_wait_for_mask()
1373 return 0; in tegra210_wait_for_mask()
1416 return 0; in tegra210_pllx_dyn_ramp()
1447 if (p < 0) in tegra210_pll_fixed_mdiv_cfg()
1462 cfg->sdm_data = 0; in tegra210_pll_fixed_mdiv_cfg()
1483 return 0; in tegra210_pll_fixed_mdiv_cfg()
1516 .divm_shift = 0,
1529 { .pdiv = 1, .hw_val = 0 },
1553 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { in pll_qlin_p_to_pdiv()
1567 { .pdiv = 1, .hw_val = 0 },
1596 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1597 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1598 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1599 { 0, 0, 0, 0, 0, 0 },
1614 .ext_misc_reg[0] = PLLX_MISC0,
1638 .divm_shift = 0,
1647 { 12000000, 510000000, 85, 1, 2, 0 },
1648 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1649 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1650 { 0, 0, 0, 0, 0, 0 },
1669 .ext_misc_reg[0] = PLLC_MISC0,
1684 .divm_shift = 0,
1712 .ext_misc_reg[0] = PLLC2_MISC0,
1742 .ext_misc_reg[0] = PLLC3_MISC0,
1753 .divm_shift = 0,
1762 { 12000000, 600000000, 50, 1, 1, 0 },
1763 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1764 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1765 { 0, 0, 0, 0, 0, 0 },
1769 { .val = 0, .div = 1 },
1784 { .val = 0, .div = 0 },
1799 .ext_misc_reg[0] = PLLC4_MISC0,
1813 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1814 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1815 { 38400000, 297600000, 93, 4, 3, 0 },
1816 { 38400000, 400000000, 125, 4, 3, 0 },
1817 { 38400000, 532800000, 111, 4, 2, 0 },
1818 { 38400000, 665600000, 104, 3, 2, 0 },
1819 { 38400000, 800000000, 125, 3, 2, 0 },
1820 { 38400000, 931200000, 97, 4, 1, 0 },
1821 { 38400000, 1065600000, 111, 4, 1, 0 },
1822 { 38400000, 1200000000, 125, 4, 1, 0 },
1823 { 38400000, 1331200000, 104, 3, 1, 0 },
1824 { 38400000, 1459200000, 76, 2, 1, 0 },
1825 { 38400000, 1600000000, 125, 3, 1, 0 },
1826 { 0, 0, 0, 0, 0, 0 },
1830 .divm_shift = 0,
1832 .override_divm_shift = 0,
1856 .ext_misc_reg[0] = PLLM_MISC2,
1882 .ext_misc_reg[0] = PLLMB_MISC1,
1895 { 672000000, 100000000, 125, 42, 0, 13 },
1896 { 624000000, 100000000, 125, 39, 0, 13 },
1897 { 336000000, 100000000, 125, 21, 0, 13 },
1898 { 312000000, 100000000, 200, 26, 0, 14 },
1899 { 38400000, 100000000, 125, 2, 0, 14 },
1900 { 12000000, 100000000, 200, 1, 0, 14 },
1901 { 0, 0, 0, 0, 0, 0 },
1905 .divm_shift = 0,
1935 { 12000000, 672000000, 56, 1, 1, 0 },
1936 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1937 { 38400000, 672000000, 70, 4, 1, 0 },
1938 { 0, 0, 0, 0, 0, 0 },
1942 .divm_shift = 0,
1962 .ext_misc_reg[0] = PLLRE_MISC0,
1975 .divm_shift = 0,
1984 { 12000000, 408000000, 34, 1, 1, 0 },
1985 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1986 { 0, 0, 0, 0, 0, 0 },
2002 .ext_misc_reg[0] = PLLP_MISC0,
2030 .ext_misc_reg[0] = PLLA1_MISC0,
2041 .divm_shift = 0,
2050 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2051 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2052 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2053 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2054 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2055 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2056 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2057 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2058 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2059 { 0, 0, 0, 0, 0, 0, 0 },
2082 .ext_misc_reg[0] = PLLA_MISC0,
2094 .divm_shift = 0,
2103 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2104 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2105 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2106 { 0, 0, 0, 0, 0, 0, 0 },
2129 .ext_misc_reg[0] = PLLD_MISC0,
2141 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2142 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2143 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2144 { 0, 0, 0, 0, 0, 0, 0 },
2166 .ssc_ctrl_reg = 0,
2167 .ssc_ctrl_en_mask = 0,
2171 .ext_misc_reg[0] = PLLD2_MISC0,
2186 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2187 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2188 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2189 { 0, 0, 0, 0, 0, 0, 0 },
2214 .ext_misc_reg[0] = PLLDP_MISC,
2229 .divm_shift = 0,
2238 { 12000000, 480000000, 40, 1, 1, 0 },
2239 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2240 { 38400000, 480000000, 25, 2, 1, 0 },
2241 { 0, 0, 0, 0, 0, 0 },
2257 .ext_misc_reg[0] = PLLU_MISC0,
2281 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2282 .stable_count = 0x0, .active_delay_count = 0x6,
2283 .xtal_freq_count = 0x80
2285 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2286 .stable_count = 0x33, .active_delay_count = 0x05,
2287 .xtal_freq_count = 0x7f
2289 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2290 .stable_count = 0x4b, .active_delay_count = 0x06,
2291 .xtal_freq_count = 0xbb
2293 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2294 .stable_count = 0x2f, .active_delay_count = 0x08,
2295 .xtal_freq_count = 0x76
2297 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2298 .stable_count = 0x66, .active_delay_count = 0x09,
2299 .xtal_freq_count = 0xfe
2301 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2302 .stable_count = 0x41, .active_delay_count = 0x0a,
2303 .xtal_freq_count = 0xa4
2614 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2704 return 0; in tegra210_clk_handle_mbist_war()
2710 if (err < 0) in tegra210_clk_handle_mbist_war()
2721 return 0; in tegra210_clk_handle_mbist_war()
2755 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { in tegra210_utmi_param_configure()
2775 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ in tegra210_utmi_param_configure()
2776 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); in tegra210_utmi_param_configure()
2779 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); in tegra210_utmi_param_configure()
2787 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); in tegra210_utmi_param_configure()
2791 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); in tegra210_utmi_param_configure()
2860 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2862 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2866 reg &= ~GENMASK(20, 0); in tegra210_enable_pllu()
2887 return 0; in tegra210_enable_pllu()
2901 if (err < 0) { in tegra210_init_pllu()
2939 return 0; in tegra210_init_pllu()
2973 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2976 { .val = 0, .div = 2 },
2980 { .val = 0, .div = 0 },
2998 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
3001 * these bits to 0b11. While not an invalid setting, code should
3002 * always set the bits to 0b01 to select sor1_pad_clkout.
3013 CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0,
3014 0, 182, 0, tegra_clk_sor0, NULL, 0,
3017 CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
3018 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
3019 NULL, 0, &sor0_lock),
3021 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
3022 TEGRA_DIVIDER_ROUND_UP, 183, 0,
3023 tegra_clk_sor1, sor1_parents_idx, 0,
3026 CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0,
3027 0, 0, TEGRA_PERIPH_NO_GATE,
3028 tegra_clk_sor1_out, NULL, 0, &sor1_lock),
3036 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
3046 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, in tegra210_periph_clk_init()
3050 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, in tegra210_periph_clk_init()
3054 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3058 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3063 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, in tegra210_periph_clk_init()
3064 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); in tegra210_periph_clk_init()
3068 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, in tegra210_periph_clk_init()
3069 clk_base, 0, 48, in tegra210_periph_clk_init()
3074 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra210_periph_clk_init()
3075 clk_base, 0, 82, in tegra210_periph_clk_init()
3082 23, 0, &pll_d_lock); in tegra210_periph_clk_init()
3089 CLK_SOURCE_LA, 0); in tegra210_periph_clk_init()
3093 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3094 0, 0, &pll_e_lock); in tegra210_periph_clk_init()
3099 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3100 1, 0, &pll_e_lock); in tegra210_periph_clk_init()
3105 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, in tegra210_periph_clk_init()
3106 0, NULL); in tegra210_periph_clk_init()
3111 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3116 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3119 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) { in tegra210_periph_clk_init()
3150 pmc, 0, &pll_c_params, NULL); in tegra210_pll_init()
3157 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3160 clk_base + PLLC_OUT, 1, 0, in tegra210_pll_init()
3161 CLK_SET_RATE_PARENT, 0, NULL); in tegra210_pll_init()
3173 pmc, 0, &pll_c2_params, NULL); in tegra210_pll_init()
3179 pmc, 0, &pll_c3_params, NULL); in tegra210_pll_init()
3209 0, 1, 1); in tegra210_pll_init()
3214 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, in tegra210_pll_init()
3221 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, in tegra210_pll_init()
3222 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3229 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3233 clk_base + PLLU_OUTA, 1, 0, in tegra210_pll_init()
3234 CLK_SET_RATE_PARENT, 0, &pll_u_lock); in tegra210_pll_init()
3240 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3245 CLK_SET_RATE_PARENT, 0, &pll_u_lock); in tegra210_pll_init()
3252 22, 0, &pll_u_lock); in tegra210_pll_init()
3259 23, 0, &pll_u_lock); in tegra210_pll_init()
3266 25, 0, &pll_u_lock); in tegra210_pll_init()
3271 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra210_pll_init()
3284 clk_base, pmc, 0, in tegra210_pll_init()
3290 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, in tegra210_pll_init()
3291 clk_base + PLLRE_BASE, 16, 5, 0, in tegra210_pll_init()
3297 clk_base + PLLRE_OUT1, 0, in tegra210_pll_init()
3301 clk_base + PLLRE_OUT1, 1, 0, in tegra210_pll_init()
3302 CLK_SET_RATE_PARENT, 0, NULL); in tegra210_pll_init()
3307 clk_base, 0, &pll_e_params, NULL); in tegra210_pll_init()
3313 0, &pll_c4_vco_params, NULL, pll_ref_freq); in tegra210_pll_init()
3318 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, in tegra210_pll_init()
3319 clk_base + PLLC4_BASE, 19, 4, 0, in tegra210_pll_init()
3338 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3341 clk_base + PLLC4_OUT, 1, 0, in tegra210_pll_init()
3342 CLK_SET_RATE_PARENT, 0, NULL); in tegra210_pll_init()
3348 0, &pll_dp_params, NULL); in tegra210_pll_init()
3354 0, &pll_d2_params, NULL); in tegra210_pll_init()
3410 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) in tegra210_clk_suspend()
3414 return 0; in tegra210_clk_suspend()
3431 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) in tegra210_clk_resume()
3497 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3498 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3499 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3500 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3501 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
3502 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
3503 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3504 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3505 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3506 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3507 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3509 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3510 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3515 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3516 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3517 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3518 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3519 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3520 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3521 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3522 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3523 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3524 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3525 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3526 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3528 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3529 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3530 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3531 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3532 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3533 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3534 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3535 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3536 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3537 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3538 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3540 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3541 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3542 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3543 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3544 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3545 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3546 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3547 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3548 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3550 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3618 return 0; in tegra210_reset_assert()
3638 return 0; in tegra210_reset_deassert()
3645 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) { in tegra210_mbist_clk_init()
3658 for (j = 0; j < num_clks; j++) { in tegra210_mbist_clk_init()
3686 clk_base = of_iomap(np, 0); in tegra210_clock_init()
3699 pmc_base = of_iomap(node, 0); in tegra210_clock_init()
3735 &osc_freq, &pll_ref_freq) < 0) in tegra210_clock_init()