1 // SPDX-License-Identifier: GPL-2.0-only
3  * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
24 #include <soc/tegra/emc.h>
46  * List of clock sources for various parents the EMC clock can have.
55 #define EMC_SRC_CLK_M 3
78 	struct tegra_emc *emc;  member
81 	struct emc_timing *timings;  member
101 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_recalc_rate()
109  * safer since things have EMC rate floors. Also don't touch parent_rate
121 	for (k = 0; k < tegra->num_timings; k++) {  in emc_determine_rate()
122 		if (tegra->timings[k].ram_code == ram_code)  in emc_determine_rate()
126 	for (t = k; t < tegra->num_timings; t++) {  in emc_determine_rate()
127 		if (tegra->timings[t].ram_code != ram_code)  in emc_determine_rate()
132 		timing = tegra->timings + i;  in emc_determine_rate()
134 		if (timing->rate < req->rate && i != t - 1)  in emc_determine_rate()
137 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
139 			req->rate = tegra->timings[i - 1].rate;  in emc_determine_rate()
143 		if (timing->rate < req->min_rate)  in emc_determine_rate()
146 		req->rate = timing->rate;  in emc_determine_rate()
151 		req->rate = timing->rate;  in emc_determine_rate()
155 	req->rate = clk_hw_get_rate(hw);  in emc_determine_rate()
166 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_get_parent()
176 	if (tegra->emc)  in emc_ensure_emc_driver()
177 		return tegra->emc;  in emc_ensure_emc_driver()
179 	if (!tegra->emc_node)  in emc_ensure_emc_driver()
182 	pdev = of_find_device_by_node(tegra->emc_node);  in emc_ensure_emc_driver()
189 	of_node_put(tegra->emc_node);  in emc_ensure_emc_driver()
190 	tegra->emc_node = NULL;  in emc_ensure_emc_driver()
192 	tegra->emc = platform_get_drvdata(pdev);  in emc_ensure_emc_driver()
193 	if (!tegra->emc) {  in emc_ensure_emc_driver()
194 		put_device(&pdev->dev);  in emc_ensure_emc_driver()
195 		pr_err("%s: cannot find EMC driver\n", __func__);  in emc_ensure_emc_driver()
199 	return tegra->emc;  in emc_ensure_emc_driver()
209 	struct tegra_emc *emc = emc_ensure_emc_driver(tegra);  in emc_set_timing()  local
211 	if (!emc)  in emc_set_timing()
212 		return -ENOENT;  in emc_set_timing()
214 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
215 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
217 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
218 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
220 			  __clk_get_name(timing->parent),  in emc_set_timing()
221 			  clk_get_rate(timing->parent),  in emc_set_timing()
222 			  timing->parent_rate);  in emc_set_timing()
223 		return -EINVAL;  in emc_set_timing()
226 	tegra->changing_timing = true;  in emc_set_timing()
228 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
231 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
237 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
243 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
245 	err = tegra_emc_prepare_timing_change(emc, timing->rate);  in emc_set_timing()
249 	spin_lock_irqsave(tegra->lock, flags);  in emc_set_timing()
251 	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
254 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
259 	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
261 	spin_unlock_irqrestore(tegra->lock, flags);  in emc_set_timing()
263 	tegra_emc_complete_timing_change(emc, timing->rate);  in emc_set_timing()
265 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
266 	clk_disable_unprepare(tegra->prev_parent);  in emc_set_timing()
268 	tegra->prev_parent = timing->parent;  in emc_set_timing()
269 	tegra->changing_timing = false;  in emc_set_timing()
276  * two timings with the same clock source has been requested. First try to
287 	for (i = timing_index+1; i < tegra->num_timings; i++) {  in get_backup_timing()
288 		timing = tegra->timings + i;  in get_backup_timing()
289 		if (timing->ram_code != ram_code)  in get_backup_timing()
292 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
294 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
298 	for (i = timing_index-1; i >= 0; --i) {  in get_backup_timing()
299 		timing = tegra->timings + i;  in get_backup_timing()
300 		if (timing->ram_code != ram_code)  in get_backup_timing()
303 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
305 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
330 	if (tegra->changing_timing)  in emc_set_rate()
333 	for (i = 0; i < tegra->num_timings; i++) {  in emc_set_rate()
334 		if (tegra->timings[i].rate == rate &&  in emc_set_rate()
335 		    tegra->timings[i].ram_code == ram_code) {  in emc_set_rate()
336 			timing = tegra->timings + i;  in emc_set_rate()
342 		pr_err("cannot switch to rate %ld without emc table\n", rate);  in emc_set_rate()
343 		return -EINVAL;  in emc_set_rate()
347 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
348 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
359 			return -EINVAL;  in emc_set_rate()
363 			 backup_timing->rate, rate);  in emc_set_rate()
384 	err = of_property_read_u32(node, "clock-frequency", &tmp);  in load_one_timing_from_dt()
390 	timing->rate = tmp;  in load_one_timing_from_dt()
392 	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);  in load_one_timing_from_dt()
398 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
400 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
401 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
403 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
406 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
408 			 __clk_get_name(timing->parent));  in load_one_timing_from_dt()
411 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
412 		clk_put(timing->parent);  in load_one_timing_from_dt()
413 		return -EINVAL;  in load_one_timing_from_dt()
416 	timing->parent_index = i;  in load_one_timing_from_dt()
425 	if (a->rate < b->rate)  in cmp_timings()
426 		return -1;  in cmp_timings()
427 	else if (a->rate == b->rate)  in cmp_timings()
443 	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);  in load_timings_from_dt()
445 	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);  in load_timings_from_dt()
446 	if (!tegra->timings)  in load_timings_from_dt()
447 		return -ENOMEM;  in load_timings_from_dt()
449 	timings_ptr = tegra->timings + tegra->num_timings;  in load_timings_from_dt()
450 	tegra->num_timings += child_count;  in load_timings_from_dt()
461 		timing->ram_code = ram_code;  in load_timings_from_dt()
489 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_emc()
491 	tegra->clk_regs = base;  in tegra_clk_register_emc()
492 	tegra->lock = lock;  in tegra_clk_register_emc()
494 	tegra->num_timings = 0;  in tegra_clk_register_emc()
497 		err = of_property_read_u32(node, "nvidia,ram-code",  in tegra_clk_register_emc()
503 		 * Store timings for all ram codes as we cannot read the  in tegra_clk_register_emc()
513 	if (tegra->num_timings == 0)  in tegra_clk_register_emc()
514 		pr_warn("%s: no memory timings registered\n", __func__);  in tegra_clk_register_emc()
516 	tegra->emc_node = of_parse_phandle(np,  in tegra_clk_register_emc()
517 			"nvidia,external-memory-controller", 0);  in tegra_clk_register_emc()
518 	if (!tegra->emc_node)  in tegra_clk_register_emc()
519 		pr_warn("%s: couldn't find node for EMC driver\n", __func__);  in tegra_clk_register_emc()
521 	init.name = "emc";  in tegra_clk_register_emc()
527 	tegra->hw.init = &init;  in tegra_clk_register_emc()
529 	clk = clk_register(NULL, &tegra->hw);  in tegra_clk_register_emc()
533 	tegra->prev_parent = clk_hw_get_parent_by_index(  in tegra_clk_register_emc()
534 		&tegra->hw, emc_get_parent(&tegra->hw))->clk;  in tegra_clk_register_emc()
535 	tegra->changing_timing = false;  in tegra_clk_register_emc()
537 	/* Allow debugging tools to see the EMC clock */  in tegra_clk_register_emc()
538 	clk_register_clkdev(clk, "emc", "tegra-clk-debug");  in tegra_clk_register_emc()