Lines Matching refs:pll_params
1199 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, in _pll_fixed_mdiv() argument
1202 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1204 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1205 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1206 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1208 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1209 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1211 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1264 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, in _setup_dynamic_ramp() argument
1293 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1294 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1295 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1867 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, in _tegra_init_pll() argument
1879 pll->params = pll_params; in _tegra_init_pll()
1882 if (!pll_params->div_nmp) in _tegra_init_pll()
1883 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1919 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pll() argument
1925 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1927 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1950 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle() argument
1956 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1958 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1959 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1961 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1975 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) in tegra_clk_register_pllu() argument
1980 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
1982 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
2042 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllxc() argument
2057 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2062 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2064 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2065 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2072 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2075 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); in tegra_clk_register_pllxc()
2079 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2080 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2083 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2085 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2087 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2091 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2106 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre() argument
2113 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2115 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2116 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2119 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2127 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2128 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2132 m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllre()
2134 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2155 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllm() argument
2162 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2174 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2176 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2177 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2180 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2181 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2182 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2197 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc() argument
2201 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2218 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2220 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2221 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2234 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllc()
2235 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2254 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2255 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2256 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2271 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra114() argument
2277 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2294 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllu_tegra114() argument
2300 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2302 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2328 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss() argument
2338 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2348 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2358 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2362 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllss()
2363 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2365 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2372 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2377 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2378 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2382 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2384 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2390 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2391 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2411 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre_tegra210() argument
2417 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2419 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2420 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2586 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra210() argument
2592 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2609 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc_tegra210() argument
2613 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2629 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2631 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2632 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2635 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2636 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2651 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss_tegra210() argument
2659 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2669 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2677 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2679 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2680 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2683 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2684 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2700 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllmb() argument
2707 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2719 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2721 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2722 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2725 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2726 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()
2727 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()