Lines Matching full:pll
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) in clk_pll_wait_for_lock()
304 lock_addr += pll->params->misc_reg; in clk_pll_wait_for_lock()
306 lock_addr += pll->params->base_reg; in clk_pll_wait_for_lock()
308 lock_mask = pll->params->lock_mask; in clk_pll_wait_for_lock()
310 for (i = 0; i < pll->params->lock_delay; i++) { in clk_pll_wait_for_lock()
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, in clk_pll_wait_for_lock()
320 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock()
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) in tegra_pll_wait_for_lock() argument
327 return clk_pll_wait_for_lock(pll); in tegra_pll_wait_for_lock()
330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll) in pllm_clk_is_gated_by_pmc() argument
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in pllm_clk_is_gated_by_pmc()
340 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_is_enabled() local
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) in clk_pll_is_enabled()
351 val = pll_readl_base(pll); in clk_pll_is_enabled()
358 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pll_enable() local
361 if (pll->params->iddq_reg) { in _clk_pll_enable()
362 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_enable()
363 val &= ~BIT(pll->params->iddq_bit_idx); in _clk_pll_enable()
364 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_enable()
368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
370 val &= ~BIT(pll->params->reset_bit_idx); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
374 clk_pll_enable_lock(pll); in _clk_pll_enable()
376 val = pll_readl_base(pll); in _clk_pll_enable()
377 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_enable()
380 pll_writel_base(val, pll); in _clk_pll_enable()
382 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_enable()
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
391 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pll_disable() local
394 val = pll_readl_base(pll); in _clk_pll_disable()
395 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_disable()
398 pll_writel_base(val, pll); in _clk_pll_disable()
400 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_disable()
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
408 val |= BIT(pll->params->reset_bit_idx); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
412 if (pll->params->iddq_reg) { in _clk_pll_disable()
413 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_disable()
414 val |= BIT(pll->params->iddq_bit_idx); in _clk_pll_disable()
415 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_disable()
420 static void pll_clk_start_ss(struct tegra_clk_pll *pll) in pll_clk_start_ss() argument
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_start_ss()
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
425 val |= pll->params->ssc_ctrl_en_mask; in pll_clk_start_ss()
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll) in pll_clk_stop_ss() argument
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_stop_ss()
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
435 val &= ~pll->params->ssc_ctrl_en_mask; in pll_clk_stop_ss()
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
442 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
449 if (pll->lock) in clk_pll_enable()
450 spin_lock_irqsave(pll->lock, flags); in clk_pll_enable()
454 ret = clk_pll_wait_for_lock(pll); in clk_pll_enable()
456 pll_clk_start_ss(pll); in clk_pll_enable()
458 if (pll->lock) in clk_pll_enable()
459 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_enable()
466 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
469 if (pll->lock) in clk_pll_disable()
470 spin_lock_irqsave(pll->lock, flags); in clk_pll_disable()
472 pll_clk_stop_ss(pll); in clk_pll_disable()
476 if (pll->lock) in clk_pll_disable()
477 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_disable()
482 struct tegra_clk_pll *pll = to_clk_pll(hw); in _p_div_to_hw() local
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _p_div_to_hw()
496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) in tegra_pll_p_div_to_hw() argument
498 return _p_div_to_hw(&pll->hw, p_div); in tegra_pll_p_div_to_hw()
503 struct tegra_clk_pll *pll = to_clk_pll(hw); in _hw_to_p_div() local
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _hw_to_p_div()
522 struct tegra_clk_pll *pll = to_clk_pll(hw); in _get_table_rate() local
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
534 if (pll->params->pdiv_tohw) { in _get_table_rate()
556 struct tegra_clk_pll *pll = to_clk_pll(hw); in _calc_rate() local
595 if (cfg->m == 0 || cfg->m > divm_max(pll) || in _calc_rate()
596 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || in _calc_rate()
597 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
604 if (pll->params->pdiv_tohw) { in _calc_rate()
618 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
627 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_set_sdm_data() local
631 if (!pll->params->sdm_din_reg) in clk_pll_set_sdm_data()
635 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); in clk_pll_set_sdm_data()
636 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); in clk_pll_set_sdm_data()
637 pll_writel_sdm_din(val, pll); in clk_pll_set_sdm_data()
640 val = pll_readl_sdm_ctrl(pll); in clk_pll_set_sdm_data()
641 enabled = (val & sdm_en_mask(pll)); in clk_pll_set_sdm_data()
644 val &= ~pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
647 val |= pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
649 pll_writel_sdm_ctrl(val, pll); in clk_pll_set_sdm_data()
652 static void _update_pll_mnp(struct tegra_clk_pll *pll, in _update_pll_mnp() argument
656 struct tegra_clk_pll_params *params = pll->params; in _update_pll_mnp()
660 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & in _update_pll_mnp()
662 val = pll_override_readl(params->pmc_divp_reg, pll); in _update_pll_mnp()
663 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); in _update_pll_mnp()
665 pll_override_writel(val, params->pmc_divp_reg, pll); in _update_pll_mnp()
667 val = pll_override_readl(params->pmc_divnm_reg, pll); in _update_pll_mnp()
668 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | in _update_pll_mnp()
669 (divn_mask(pll) << div_nmp->override_divn_shift)); in _update_pll_mnp()
672 pll_override_writel(val, params->pmc_divnm_reg, pll); in _update_pll_mnp()
674 val = pll_readl_base(pll); in _update_pll_mnp()
676 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | in _update_pll_mnp()
677 divp_mask_shifted(pll)); in _update_pll_mnp()
679 val |= (cfg->m << divm_shift(pll)) | in _update_pll_mnp()
680 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
681 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
683 pll_writel_base(val, pll); in _update_pll_mnp()
685 clk_pll_set_sdm_data(&pll->hw, cfg); in _update_pll_mnp()
689 static void _get_pll_mnp(struct tegra_clk_pll *pll, in _get_pll_mnp() argument
693 struct tegra_clk_pll_params *params = pll->params; in _get_pll_mnp()
699 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & in _get_pll_mnp()
701 val = pll_override_readl(params->pmc_divp_reg, pll); in _get_pll_mnp()
702 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); in _get_pll_mnp()
704 val = pll_override_readl(params->pmc_divnm_reg, pll); in _get_pll_mnp()
705 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); in _get_pll_mnp()
706 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); in _get_pll_mnp()
708 val = pll_readl_base(pll); in _get_pll_mnp()
710 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); in _get_pll_mnp()
711 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
712 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
714 if (pll->params->sdm_din_reg) { in _get_pll_mnp()
715 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { in _get_pll_mnp()
716 val = pll_readl_sdm_din(pll); in _get_pll_mnp()
717 val &= sdm_din_mask(pll); in _get_pll_mnp()
724 static void _update_pll_cpcon(struct tegra_clk_pll *pll, in _update_pll_cpcon() argument
730 val = pll_readl_misc(pll); in _update_pll_cpcon()
735 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { in _update_pll_cpcon()
739 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { in _update_pll_cpcon()
741 if (rate >= (pll->params->vco_max >> 1)) in _update_pll_cpcon()
745 pll_writel_misc(val, pll); in _update_pll_cpcon()
751 struct tegra_clk_pll *pll = to_clk_pll(hw); in _program_pll() local
757 if (state && pll->params->pre_rate_change) { in _program_pll()
758 ret = pll->params->pre_rate_change(); in _program_pll()
763 _get_pll_mnp(pll, &old_cfg); in _program_pll()
765 if (state && pll->params->defaults_set && pll->params->dyn_ramp && in _program_pll()
767 ret = pll->params->dyn_ramp(pll, cfg); in _program_pll()
773 pll_clk_stop_ss(pll); in _program_pll()
777 if (!pll->params->defaults_set && pll->params->set_defaults) in _program_pll()
778 pll->params->set_defaults(pll); in _program_pll()
780 _update_pll_mnp(pll, cfg); in _program_pll()
782 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) in _program_pll()
783 _update_pll_cpcon(pll, cfg, rate); in _program_pll()
787 ret = clk_pll_wait_for_lock(pll); in _program_pll()
788 pll_clk_start_ss(pll); in _program_pll()
792 if (state && pll->params->post_rate_change) in _program_pll()
793 pll->params->post_rate_change(); in _program_pll()
801 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate() local
806 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_set_rate()
807 if (rate != pll->params->fixed_rate) { in clk_pll_set_rate()
810 pll->params->fixed_rate, rate); in clk_pll_set_rate()
817 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
823 if (pll->lock) in clk_pll_set_rate()
824 spin_lock_irqsave(pll->lock, flags); in clk_pll_set_rate()
826 _get_pll_mnp(pll, &old_cfg); in clk_pll_set_rate()
827 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pll_set_rate()
834 if (pll->lock) in clk_pll_set_rate()
835 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_set_rate()
843 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate() local
846 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_round_rate()
848 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) in clk_pll_round_rate()
850 return pll->params->fixed_rate; in clk_pll_round_rate()
854 pll->params->calc_rate(hw, &cfg, rate, *prate)) in clk_pll_round_rate()
863 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
869 val = pll_readl_base(pll); in clk_pll_recalc_rate()
871 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) in clk_pll_recalc_rate()
874 if ((pll->params->flags & TEGRA_PLL_FIXED) && in clk_pll_recalc_rate()
875 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in clk_pll_recalc_rate()
878 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, in clk_pll_recalc_rate()
884 return pll->params->fixed_rate; in clk_pll_recalc_rate()
887 _get_pll_mnp(pll, &cfg); in clk_pll_recalc_rate()
889 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { in clk_pll_recalc_rate()
900 if (pll->params->set_gain) in clk_pll_recalc_rate()
901 pll->params->set_gain(&cfg); in clk_pll_recalc_rate()
911 static int clk_plle_training(struct tegra_clk_pll *pll) in clk_plle_training() argument
916 if (!pll->pmc) in clk_plle_training()
923 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
925 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
927 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
929 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
931 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
933 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
935 val = pll_readl_misc(pll); in clk_plle_training()
939 val = pll_readl_misc(pll); in clk_plle_training()
954 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_enable() local
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
970 val = pll_readl_misc(pll); in clk_plle_enable()
972 pll_writel_misc(val, pll); in clk_plle_enable()
974 val = pll_readl_misc(pll); in clk_plle_enable()
976 err = clk_plle_training(pll); in clk_plle_enable()
981 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { in clk_plle_enable()
983 val = pll_readl_base(pll); in clk_plle_enable()
984 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_enable()
985 divm_mask_shifted(pll)); in clk_plle_enable()
987 val |= sel.m << divm_shift(pll); in clk_plle_enable()
988 val |= sel.n << divn_shift(pll); in clk_plle_enable()
989 val |= sel.p << divp_shift(pll); in clk_plle_enable()
991 pll_writel_base(val, pll); in clk_plle_enable()
994 val = pll_readl_misc(pll); in clk_plle_enable()
997 pll_writel_misc(val, pll); in clk_plle_enable()
999 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1002 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1004 val = pll_readl_base(pll); in clk_plle_enable()
1006 pll_writel_base(val, pll); in clk_plle_enable()
1008 clk_pll_wait_for_lock(pll); in clk_plle_enable()
1016 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_recalc_rate() local
1017 u32 val = pll_readl_base(pll); in clk_plle_recalc_rate()
1021 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1023 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1033 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_clk_pll_restore_context() local
1041 if (pll->params->set_defaults) in tegra_clk_pll_restore_context()
1042 pll->params->set_defaults(pll); in tegra_clk_pll_restore_context()
1075 /* UTMIP PLL Enable Delay Count */
1077 /* UTMIP PLL Stable count */
1079 /* UTMIP PLL Active delay count */
1081 /* UTMIP PLL Xtal frequency count */
1115 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllu_enable() local
1131 if (pll->lock) in clk_pllu_enable()
1132 spin_lock_irqsave(pll->lock, flags); in clk_pllu_enable()
1137 ret = clk_pll_wait_for_lock(pll); in clk_pllu_enable()
1155 value = pll_readl_base(pll); in clk_pllu_enable()
1157 pll_writel_base(value, pll); in clk_pllu_enable()
1159 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1160 /* Program UTMIP PLL stable and active counts */ in clk_pllu_enable()
1165 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_enable()
1169 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1171 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1172 /* Program UTMIP PLL delay and oscillator frequency counts */ in clk_pllu_enable()
1177 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_enable()
1181 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1184 if (pll->lock) in clk_pllu_enable()
1185 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_enable()
1221 struct tegra_clk_pll *pll = to_clk_pll(hw); in _calc_dynamic_ramp_rate() local
1228 p = DIV_ROUND_UP(pll->params->vco_min, rate); in _calc_dynamic_ramp_rate()
1229 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); in _calc_dynamic_ramp_rate()
1240 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) in _calc_dynamic_ramp_rate()
1253 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_pll_get_fixed_mdiv() local
1255 return (u16)_pll_fixed_mdiv(pll->params, input_rate); in tegra_pll_get_fixed_mdiv()
1304 struct tegra_clk_pll *pll = to_clk_pll(hw); in _pll_ramp_calc_pll() local
1311 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { in _pll_ramp_calc_pll()
1318 if (cfg->p > pll->params->max_p) in _pll_ramp_calc_pll()
1328 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllxc_set_rate() local
1337 if (pll->lock) in clk_pllxc_set_rate()
1338 spin_lock_irqsave(pll->lock, flags); in clk_pllxc_set_rate()
1340 _get_pll_mnp(pll, &old_cfg); in clk_pllxc_set_rate()
1341 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pllxc_set_rate()
1347 if (pll->lock) in clk_pllxc_set_rate()
1348 spin_unlock_irqrestore(pll->lock, flags); in clk_pllxc_set_rate()
1356 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_ramp_round_rate() local
1369 if (pll->params->set_gain) in clk_pll_ramp_round_rate()
1370 pll->params->set_gain(&cfg); in clk_pll_ramp_round_rate()
1378 static void _pllcx_strobe(struct tegra_clk_pll *pll) in _pllcx_strobe() argument
1382 val = pll_readl_misc(pll); in _pllcx_strobe()
1384 pll_writel_misc(val, pll); in _pllcx_strobe()
1388 pll_writel_misc(val, pll); in _pllcx_strobe()
1393 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_enable() local
1401 if (pll->lock) in clk_pllc_enable()
1402 spin_lock_irqsave(pll->lock, flags); in clk_pllc_enable()
1407 val = pll_readl_misc(pll); in clk_pllc_enable()
1409 pll_writel_misc(val, pll); in clk_pllc_enable()
1412 _pllcx_strobe(pll); in clk_pllc_enable()
1414 ret = clk_pll_wait_for_lock(pll); in clk_pllc_enable()
1416 if (pll->lock) in clk_pllc_enable()
1417 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_enable()
1424 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pllc_disable() local
1429 val = pll_readl_misc(pll); in _clk_pllc_disable()
1431 pll_writel_misc(val, pll); in _clk_pllc_disable()
1437 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_disable() local
1440 if (pll->lock) in clk_pllc_disable()
1441 spin_lock_irqsave(pll->lock, flags); in clk_pllc_disable()
1445 if (pll->lock) in clk_pllc_disable()
1446 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_disable()
1449 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, in _pllcx_update_dynamic_coef() argument
1474 val = pll_readl_misc(pll); in _pllcx_update_dynamic_coef()
1478 pll_writel_misc(val, pll); in _pllcx_update_dynamic_coef()
1487 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_set_rate() local
1491 if (pll->lock) in clk_pllc_set_rate()
1492 spin_lock_irqsave(pll->lock, flags); in clk_pllc_set_rate()
1498 _get_pll_mnp(pll, &old_cfg); in clk_pllc_set_rate()
1512 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); in clk_pllc_set_rate()
1516 _update_pll_mnp(pll, &cfg); in clk_pllc_set_rate()
1522 if (pll->lock) in clk_pllc_set_rate()
1523 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_set_rate()
1528 static long _pllre_calc_rate(struct tegra_clk_pll *pll, in _pllre_calc_rate() argument
1535 m = _pll_fixed_mdiv(pll->params, parent_rate); in _pllre_calc_rate()
1553 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_set_rate() local
1557 if (pll->lock) in clk_pllre_set_rate()
1558 spin_lock_irqsave(pll->lock, flags); in clk_pllre_set_rate()
1560 _pllre_calc_rate(pll, &cfg, rate, parent_rate); in clk_pllre_set_rate()
1561 _get_pll_mnp(pll, &old_cfg); in clk_pllre_set_rate()
1569 _update_pll_mnp(pll, &cfg); in clk_pllre_set_rate()
1573 ret = clk_pll_wait_for_lock(pll); in clk_pllre_set_rate()
1577 if (pll->lock) in clk_pllre_set_rate()
1578 spin_unlock_irqrestore(pll->lock, flags); in clk_pllre_set_rate()
1587 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_recalc_rate() local
1590 _get_pll_mnp(pll, &cfg); in clk_pllre_recalc_rate()
1601 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_round_rate() local
1603 return _pllre_calc_rate(pll, NULL, rate, *prate); in clk_pllre_round_rate()
1608 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra114_enable() local
1617 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra114_enable()
1620 if (pll->lock) in clk_plle_tegra114_enable()
1621 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_enable()
1623 val = pll_readl_base(pll); in clk_plle_tegra114_enable()
1625 pll_writel_base(val, pll); in clk_plle_tegra114_enable()
1627 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1630 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1633 val = pll_readl_misc(pll); in clk_plle_tegra114_enable()
1639 pll_writel_misc(val, pll); in clk_plle_tegra114_enable()
1642 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1644 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1646 val = pll_readl_base(pll); in clk_plle_tegra114_enable()
1647 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_tegra114_enable()
1648 divm_mask_shifted(pll)); in clk_plle_tegra114_enable()
1650 val |= sel.m << divm_shift(pll); in clk_plle_tegra114_enable()
1651 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1653 pll_writel_base(val, pll); in clk_plle_tegra114_enable()
1657 ret = clk_pll_wait_for_lock(pll); in clk_plle_tegra114_enable()
1662 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1666 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1668 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1671 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1674 /* Enable HW control of XUSB brick PLL */ in clk_plle_tegra114_enable()
1675 val = pll_readl_misc(pll); in clk_plle_tegra114_enable()
1677 pll_writel_misc(val, pll); in clk_plle_tegra114_enable()
1679 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1682 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1685 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1687 val = pll_readl(XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1692 pll_writel(val, XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1695 pll_writel(val, XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1697 /* Enable HW control of SATA PLL */ in clk_plle_tegra114_enable()
1698 val = pll_readl(SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1702 pll_writel(val, SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1706 val = pll_readl(SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1708 pll_writel(val, SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1711 if (pll->lock) in clk_plle_tegra114_enable()
1712 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_enable()
1719 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra114_disable() local
1723 if (pll->lock) in clk_plle_tegra114_disable()
1724 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_disable()
1728 val = pll_readl_misc(pll); in clk_plle_tegra114_disable()
1730 pll_writel_misc(val, pll); in clk_plle_tegra114_disable()
1733 if (pll->lock) in clk_plle_tegra114_disable()
1734 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_disable()
1739 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllu_tegra114_enable() local
1754 if (pll->lock) in clk_pllu_tegra114_enable()
1755 spin_lock_irqsave(pll->lock, flags); in clk_pllu_tegra114_enable()
1760 ret = clk_pll_wait_for_lock(pll); in clk_pllu_tegra114_enable()
1778 value = pll_readl_base(pll); in clk_pllu_tegra114_enable()
1780 pll_writel_base(value, pll); in clk_pllu_tegra114_enable()
1782 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1783 /* Program UTMIP PLL stable and active counts */ in clk_pllu_tegra114_enable()
1788 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_tegra114_enable()
1792 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1794 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1795 /* Program UTMIP PLL delay and oscillator frequency counts */ in clk_pllu_tegra114_enable()
1800 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_tegra114_enable()
1805 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1808 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1812 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1814 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1817 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1825 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1828 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1833 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1835 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1838 if (pll->lock) in clk_pllu_tegra114_enable()
1839 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_tegra114_enable()
1844 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) in _clk_plle_tegra_init_parent() argument
1849 val = pll_readl_base(pll); in _clk_plle_tegra_init_parent()
1850 val_aux = pll_readl(pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1860 pll_writel(val_aux, pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1861 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1870 struct tegra_clk_pll *pll; in _tegra_init_pll() local
1872 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _tegra_init_pll()
1873 if (!pll) in _tegra_init_pll()
1876 pll->clk_base = clk_base; in _tegra_init_pll()
1877 pll->pmc = pmc; in _tegra_init_pll()
1879 pll->params = pll_params; in _tegra_init_pll()
1880 pll->lock = lock; in _tegra_init_pll()
1885 return pll; in _tegra_init_pll()
1888 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, in _tegra_clk_register_pll() argument
1901 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1902 if (pll->params->flags & TEGRA_PLLM) in _tegra_clk_register_pll()
1903 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1905 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
1908 if (pll->params->set_defaults) in _tegra_clk_register_pll()
1909 pll->params->set_defaults(pll); in _tegra_clk_register_pll()
1912 pll->hw.init = &init; in _tegra_clk_register_pll()
1914 return clk_register(NULL, &pll->hw); in _tegra_clk_register_pll()
1922 struct tegra_clk_pll *pll; in tegra_clk_register_pll() local
1927 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1928 if (IS_ERR(pll)) in tegra_clk_register_pll()
1929 return ERR_CAST(pll); in tegra_clk_register_pll()
1931 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pll()
1934 kfree(pll); in tegra_clk_register_pll()
1953 struct tegra_clk_pll *pll; in tegra_clk_register_plle() local
1961 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1962 if (IS_ERR(pll)) in tegra_clk_register_plle()
1963 return ERR_CAST(pll); in tegra_clk_register_plle()
1965 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle()
1968 kfree(pll); in tegra_clk_register_plle()
1977 struct tegra_clk_pll *pll; in tegra_clk_register_pllu() local
1982 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
1983 if (IS_ERR(pll)) in tegra_clk_register_pllu()
1984 return ERR_CAST(pll); in tegra_clk_register_pllu()
1986 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu()
1989 kfree(pll); in tegra_clk_register_pllu()
2045 struct tegra_clk_pll *pll; in tegra_clk_register_pllxc() local
2069 * If the pll has a set_defaults callback, it will take care of in tegra_clk_register_pllxc()
2091 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2092 if (IS_ERR(pll)) in tegra_clk_register_pllxc()
2093 return ERR_CAST(pll); in tegra_clk_register_pllxc()
2095 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllxc()
2098 kfree(pll); in tegra_clk_register_pllxc()
2110 struct tegra_clk_pll *pll; in tegra_clk_register_pllre() local
2119 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2120 if (IS_ERR(pll)) in tegra_clk_register_pllre()
2121 return ERR_CAST(pll); in tegra_clk_register_pllre()
2125 val = pll_readl_base(pll); in tegra_clk_register_pllre()
2133 val = m << divm_shift(pll); in tegra_clk_register_pllre()
2134 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2135 pll_writel_base(val, pll); in tegra_clk_register_pllre()
2140 val = pll_readl_misc(pll); in tegra_clk_register_pllre()
2142 pll_writel_misc(val, pll); in tegra_clk_register_pllre()
2144 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre()
2147 kfree(pll); in tegra_clk_register_pllre()
2158 struct tegra_clk_pll *pll; in tegra_clk_register_pllm() local
2182 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2183 if (IS_ERR(pll)) in tegra_clk_register_pllm()
2184 return ERR_CAST(pll); in tegra_clk_register_pllm()
2186 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllm()
2189 kfree(pll); in tegra_clk_register_pllm()
2202 struct tegra_clk_pll *pll; in tegra_clk_register_pllc() local
2221 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2222 if (IS_ERR(pll)) in tegra_clk_register_pllc()
2223 return ERR_CAST(pll); in tegra_clk_register_pllc()
2227 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. in tegra_clk_register_pllc()
2228 * Initialize PLL to default state: disabled, reset; shadow registers in tegra_clk_register_pllc()
2250 pll_writel_base(0, pll); in tegra_clk_register_pllc()
2251 _update_pll_mnp(pll, &cfg); in tegra_clk_register_pllc()
2253 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); in tegra_clk_register_pllc()
2254 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2255 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2256 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2258 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); in tegra_clk_register_pllc()
2260 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc()
2263 kfree(pll); in tegra_clk_register_pllc()
2274 struct tegra_clk_pll *pll; in tegra_clk_register_plle_tegra114() local
2277 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2278 if (IS_ERR(pll)) in tegra_clk_register_plle_tegra114()
2279 return ERR_CAST(pll); in tegra_clk_register_plle_tegra114()
2281 _clk_plle_tegra_init_parent(pll); in tegra_clk_register_plle_tegra114()
2283 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra114()
2286 kfree(pll); in tegra_clk_register_plle_tegra114()
2297 struct tegra_clk_pll *pll; in tegra_clk_register_pllu_tegra114() local
2302 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2303 if (IS_ERR(pll)) in tegra_clk_register_pllu_tegra114()
2304 return ERR_CAST(pll); in tegra_clk_register_pllu_tegra114()
2306 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu_tegra114()
2309 kfree(pll); in tegra_clk_register_pllu_tegra114()
2331 struct tegra_clk_pll *pll; in tegra_clk_register_pllss() local
2348 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2349 if (IS_ERR(pll)) in tegra_clk_register_pllss()
2350 return ERR_CAST(pll); in tegra_clk_register_pllss()
2352 val = pll_readl_base(pll); in tegra_clk_register_pllss()
2354 pll_writel_base(val, pll); in tegra_clk_register_pllss()
2360 /* initialize PLL to minimum rate */ in tegra_clk_register_pllss()
2368 kfree(pll); in tegra_clk_register_pllss()
2374 _update_pll_mnp(pll, &cfg); in tegra_clk_register_pllss()
2376 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); in tegra_clk_register_pllss()
2377 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2378 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2381 val = pll_readl_base(pll); in tegra_clk_register_pllss()
2386 kfree(pll); in tegra_clk_register_pllss()
2395 pll_writel_base(val, pll); in tegra_clk_register_pllss()
2397 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss()
2401 kfree(pll); in tegra_clk_register_pllss()
2414 struct tegra_clk_pll *pll; in tegra_clk_register_pllre_tegra210() local
2423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2424 if (IS_ERR(pll)) in tegra_clk_register_pllre_tegra210()
2425 return ERR_CAST(pll); in tegra_clk_register_pllre_tegra210()
2427 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre_tegra210()
2430 kfree(pll); in tegra_clk_register_pllre_tegra210()
2437 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_is_enabled() local
2440 val = pll_readl_base(pll); in clk_plle_tegra210_is_enabled()
2447 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_enable() local
2459 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra210_enable()
2462 if (pll->lock) in clk_plle_tegra210_enable()
2463 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_enable()
2465 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2469 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2471 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2473 val = pll_readl_misc(pll); in clk_plle_tegra210_enable()
2479 pll_writel_misc(val, pll); in clk_plle_tegra210_enable()
2482 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2484 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2486 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2487 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_tegra210_enable()
2488 divm_mask_shifted(pll)); in clk_plle_tegra210_enable()
2490 val |= sel.m << divm_shift(pll); in clk_plle_tegra210_enable()
2491 val |= sel.n << divn_shift(pll); in clk_plle_tegra210_enable()
2493 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2496 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2498 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2500 ret = clk_pll_wait_for_lock(pll); in clk_plle_tegra210_enable()
2505 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2509 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2511 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2514 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2517 val = pll_readl_misc(pll); in clk_plle_tegra210_enable()
2519 pll_writel_misc(val, pll); in clk_plle_tegra210_enable()
2521 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2524 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2527 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2530 if (pll->lock) in clk_plle_tegra210_enable()
2531 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_enable()
2538 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_disable() local
2542 if (pll->lock) in clk_plle_tegra210_disable()
2543 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_disable()
2546 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2550 val = pll_readl_base(pll); in clk_plle_tegra210_disable()
2552 pll_writel_base(val, pll); in clk_plle_tegra210_disable()
2554 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2556 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2558 val = pll_readl_misc(pll); in clk_plle_tegra210_disable()
2560 pll_writel_misc(val, pll); in clk_plle_tegra210_disable()
2564 if (pll->lock) in clk_plle_tegra210_disable()
2565 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_disable()
2570 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_clk_plle_t210_restore_context() local
2572 _clk_plle_tegra_init_parent(pll); in tegra_clk_plle_t210_restore_context()
2589 struct tegra_clk_pll *pll; in tegra_clk_register_plle_tegra210() local
2592 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2593 if (IS_ERR(pll)) in tegra_clk_register_plle_tegra210()
2594 return ERR_CAST(pll); in tegra_clk_register_plle_tegra210()
2596 _clk_plle_tegra_init_parent(pll); in tegra_clk_register_plle_tegra210()
2598 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra210()
2601 kfree(pll); in tegra_clk_register_plle_tegra210()
2614 struct tegra_clk_pll *pll; in tegra_clk_register_pllc_tegra210() local
2636 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2637 if (IS_ERR(pll)) in tegra_clk_register_pllc_tegra210()
2638 return ERR_CAST(pll); in tegra_clk_register_pllc_tegra210()
2640 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc_tegra210()
2643 kfree(pll); in tegra_clk_register_pllc_tegra210()
2654 struct tegra_clk_pll *pll; in tegra_clk_register_pllss_tegra210() local
2684 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2685 if (IS_ERR(pll)) in tegra_clk_register_pllss_tegra210()
2686 return ERR_CAST(pll); in tegra_clk_register_pllss_tegra210()
2688 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss_tegra210()
2692 kfree(pll); in tegra_clk_register_pllss_tegra210()
2703 struct tegra_clk_pll *pll; in tegra_clk_register_pllmb() local
2727 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()
2728 if (IS_ERR(pll)) in tegra_clk_register_pllmb()
2729 return ERR_CAST(pll); in tegra_clk_register_pllmb()
2731 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllmb()
2734 kfree(pll); in tegra_clk_register_pllmb()