Lines Matching full:ahb1
221 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
236 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
247 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
249 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
251 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
253 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
255 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
257 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
259 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
261 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
263 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
265 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
267 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
269 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
271 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
273 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
275 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
277 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
279 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
281 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
283 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
285 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
287 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
289 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
291 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
294 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
296 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
298 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
300 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
302 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
304 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
306 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
308 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
310 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
312 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
314 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
316 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
318 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
320 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
322 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
733 "axi", "ahb1" };
1250 /* Force AHB1 to PLL6 / 3 */ in sun6i_a31_ccu_setup()