24  * PLL configuration register bits for PLL3200 C32
35  * PLL configuration register bits for PLL4600 C28
124  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
134  * PLL clock that is integrated in the ClockGenA instances on the STiH415
138  * @type: PLL instance type.
139  * @regs_base: base of the PLL configuration register(s).
168 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_is_locked()  local
169 	u32 locked = CLKGEN_READ(pll, locked_status);  in clkgen_pll_is_locked()
176 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_is_enabled()  local
177 	u32 poweroff = CLKGEN_READ(pll, pdn_status);  in clkgen_pll_is_enabled()
183 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in __clkgen_pll_enable()  local
184 	void __iomem *base =  pll->regs_base;  in __clkgen_pll_enable()
185 	struct clkgen_field *field = &pll->data->locked_status;  in __clkgen_pll_enable()
192 	CLKGEN_WRITE(pll, pdn_ctrl, 0);  in __clkgen_pll_enable()
198 		if (pll->data->switch2pll_en)  in __clkgen_pll_enable()
199 			CLKGEN_WRITE(pll, switch2pll, 0);  in __clkgen_pll_enable()
209 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_enable()  local
213 	if (pll->lock)  in clkgen_pll_enable()
214 		spin_lock_irqsave(pll->lock, flags);  in clkgen_pll_enable()
218 	if (pll->lock)  in clkgen_pll_enable()
219 		spin_unlock_irqrestore(pll->lock, flags);  in clkgen_pll_enable()
226 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in __clkgen_pll_disable()  local
231 	if (pll->data->switch2pll_en)  in __clkgen_pll_disable()
232 		CLKGEN_WRITE(pll, switch2pll, 1);  in __clkgen_pll_disable()
234 	CLKGEN_WRITE(pll, pdn_ctrl, 1);  in __clkgen_pll_disable()
241 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_disable()  local
244 	if (pll->lock)  in clkgen_pll_disable()
245 		spin_lock_irqsave(pll->lock, flags);  in clkgen_pll_disable()
249 	if (pll->lock)  in clkgen_pll_disable()
250 		spin_unlock_irqrestore(pll->lock, flags);  in clkgen_pll_disable()
254 			  struct stm_pll *pll)  in clk_pll3200c32_get_params()  argument
287 			pll->idf  = i;  in clk_pll3200c32_get_params()
288 			pll->ndiv = n;  in clk_pll3200c32_get_params()
297 	for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)  in clk_pll3200c32_get_params()
303 static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,  in clk_pll3200c32_get_rate()  argument
306 	if (!pll->idf)  in clk_pll3200c32_get_rate()
307 		pll->idf = 1;  in clk_pll3200c32_get_rate()
309 	*rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;  in clk_pll3200c32_get_rate()
317 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in recalc_stm_pll3200c32()  local
324 	ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll3200c32()
325 	idf = CLKGEN_READ(pll, idf);  in recalc_stm_pll3200c32()
360 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in set_rate_stm_pll3200c32()  local
379 	pll->ndiv = params.ndiv;  in set_rate_stm_pll3200c32()
380 	pll->idf = params.idf;  in set_rate_stm_pll3200c32()
381 	pll->cp = params.cp;  in set_rate_stm_pll3200c32()
385 	if (pll->lock)  in set_rate_stm_pll3200c32()
386 		spin_lock_irqsave(pll->lock, flags);  in set_rate_stm_pll3200c32()
388 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll3200c32()
389 	CLKGEN_WRITE(pll, idf, pll->idf);  in set_rate_stm_pll3200c32()
390 	CLKGEN_WRITE(pll, cp, pll->cp);  in set_rate_stm_pll3200c32()
392 	if (pll->lock)  in set_rate_stm_pll3200c32()
393 		spin_unlock_irqrestore(pll->lock, flags);  in set_rate_stm_pll3200c32()
400 /* PLL output structure
415 			  struct stm_pll *pll)  in clk_pll4600c28_get_params()  argument
446 				pll->idf  = i;  in clk_pll4600c28_get_params()
447 				pll->ndiv = n;  in clk_pll4600c28_get_params()
459 static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,  in clk_pll4600c28_get_rate()  argument
462 	if (!pll->idf)  in clk_pll4600c28_get_rate()
463 		pll->idf = 1;  in clk_pll4600c28_get_rate()
465 	*rate = (input / pll->idf) * 2 * pll->ndiv;  in clk_pll4600c28_get_rate()
473 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in recalc_stm_pll4600c28()  local
480 	params.ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll4600c28()
481 	params.idf = CLKGEN_READ(pll, idf);  in recalc_stm_pll4600c28()
514 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in set_rate_stm_pll4600c28()  local
538 	pll->ndiv = params.ndiv;  in set_rate_stm_pll4600c28()
539 	pll->idf = params.idf;  in set_rate_stm_pll4600c28()
543 	if (pll->lock)  in set_rate_stm_pll4600c28()
544 		spin_lock_irqsave(pll->lock, flags);  in set_rate_stm_pll4600c28()
546 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll4600c28()
547 	CLKGEN_WRITE(pll, idf, pll->idf);  in set_rate_stm_pll4600c28()
549 	if (pll->lock)  in set_rate_stm_pll4600c28()
550 		spin_unlock_irqrestore(pll->lock, flags);  in set_rate_stm_pll4600c28()
587 	struct clkgen_pll *pll;  in clkgen_pll_register()  local
591 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in clkgen_pll_register()
592 	if (!pll)  in clkgen_pll_register()
602 	pll->data = pll_data;  in clkgen_pll_register()
603 	pll->regs_base = reg;  in clkgen_pll_register()
604 	pll->hw.init = &init;  in clkgen_pll_register()
605 	pll->lock = lock;  in clkgen_pll_register()
607 	clk = clk_register(NULL, &pll->hw);  in clkgen_pll_register()
609 		kfree(pll);  in clkgen_pll_register()