35 	unsigned short regofs;  /* register offset */  member
43 	unsigned short regofs;  /* register offset */  member
78 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -  in pll_clk_recalc_rate()
86 		u32 cfg0 = clkc_readl(clk->regofs);  in pll_clk_recalc_rate()
150 	clkc_writel(reg, clk->regofs);  in pll_clk_set_rate()
152 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
155 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
218 	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
225 	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
232 	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
299 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_get_parent()
314 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_set_parent()
322 	clkc_writel(cfg | parent, clk->regofs);  in dmn_clk_set_parent()
324 	while (clkc_readl(clk->regofs) & BIT(3))  in dmn_clk_set_parent()
337 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_recalc_rate()
395 	reg = clkc_readl(clk->regofs);  in dmn_clk_set_rate()
398 	clkc_writel(reg, clk->regofs);  in dmn_clk_set_rate()
401 	while (clkc_readl(clk->regofs) & BIT(25))  in dmn_clk_set_rate()
459 	.regofs = SIRFSOC_CLKC_MEM_CFG,
474 	.regofs = SIRFSOC_CLKC_SYS_CFG,
488 	.regofs = SIRFSOC_CLKC_IO_CFG,
511 	.regofs = SIRFSOC_CLKC_CPU_CFG,
538 	.regofs = SIRFSOC_CLKC_DSP_CFG,
553 	.regofs = SIRFSOC_CLKC_GFX_CFG,
568 	.regofs = SIRFSOC_CLKC_MM_CFG,
588 	.regofs = SIRFSOC_CLKC_LCD_CFG,
603 	.regofs = SIRFSOC_CLKC_LCD_CFG,