6  * This file contains the utility functions to register the pll clocks.
16 #include "clk-pll.h"
24 	/* PLL enable control bit offset in @con_reg register */
26 	/* PLL lock status bit offset in @con_reg register */
36 				struct samsung_clk_pll *pll, unsigned long rate)  in samsung_get_pll_settings()  argument
38 	const struct samsung_pll_rate_table  *rate_table = pll->rate_table;  in samsung_get_pll_settings()
41 	for (i = 0; i < pll->rate_count; i++) {  in samsung_get_pll_settings()
52 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll_round_rate()  local
53 	const struct samsung_pll_rate_table *rate_table = pll->rate_table;  in samsung_pll_round_rate()
57 	for (i = 0; i < pll->rate_count; i++) {  in samsung_pll_round_rate()
68 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll3xxx_enable()  local
71 	tmp = readl_relaxed(pll->con_reg);  in samsung_pll3xxx_enable()
72 	tmp |= BIT(pll->enable_offs);  in samsung_pll3xxx_enable()
73 	writel_relaxed(tmp, pll->con_reg);  in samsung_pll3xxx_enable()
78 		tmp = readl_relaxed(pll->con_reg);  in samsung_pll3xxx_enable()
79 	} while (!(tmp & BIT(pll->lock_offs)));  in samsung_pll3xxx_enable()
86 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll3xxx_disable()  local
89 	tmp = readl_relaxed(pll->con_reg);  in samsung_pll3xxx_disable()
90 	tmp &= ~BIT(pll->enable_offs);  in samsung_pll3xxx_disable()
91 	writel_relaxed(tmp, pll->con_reg);  in samsung_pll3xxx_disable()
108 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2126_recalc_rate()  local
112 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll2126_recalc_rate()
141 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll3000_recalc_rate()  local
145 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll3000_recalc_rate()
178 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll35xx_recalc_rate()  local
182 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll35xx_recalc_rate()
207 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll35xx_set_rate()  local
212 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll35xx_set_rate()
214 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll35xx_set_rate()
219 	tmp = readl_relaxed(pll->con_reg);  in samsung_pll35xx_set_rate()
225 		writel_relaxed(tmp, pll->con_reg);  in samsung_pll35xx_set_rate()
230 	/* Set PLL lock time. */  in samsung_pll35xx_set_rate()
232 			pll->lock_reg);  in samsung_pll35xx_set_rate()
234 	/* Change PLL PMS values */  in samsung_pll35xx_set_rate()
241 	writel_relaxed(tmp, pll->con_reg);  in samsung_pll35xx_set_rate()
243 	/* Wait until the PLL is locked if it is enabled. */  in samsung_pll35xx_set_rate()
244 	if (tmp & BIT(pll->enable_offs)) {  in samsung_pll35xx_set_rate()
247 			tmp = readl_relaxed(pll->con_reg);  in samsung_pll35xx_set_rate()
248 		} while (!(tmp & BIT(pll->lock_offs)));  in samsung_pll35xx_set_rate()
285 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll36xx_recalc_rate()  local
290 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll36xx_recalc_rate()
291 	pll_con1 = readl_relaxed(pll->con_reg + 4);  in samsung_pll36xx_recalc_rate()
320 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll36xx_set_rate()  local
324 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll36xx_set_rate()
326 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll36xx_set_rate()
331 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll36xx_set_rate()
332 	pll_con1 = readl_relaxed(pll->con_reg + 4);  in samsung_pll36xx_set_rate()
338 		writel_relaxed(pll_con0, pll->con_reg);  in samsung_pll36xx_set_rate()
343 	/* Set PLL lock time. */  in samsung_pll36xx_set_rate()
344 	writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);  in samsung_pll36xx_set_rate()
346 	 /* Change PLL PMS values */  in samsung_pll36xx_set_rate()
353 	writel_relaxed(pll_con0, pll->con_reg);  in samsung_pll36xx_set_rate()
357 	writel_relaxed(pll_con1, pll->con_reg + 4);  in samsung_pll36xx_set_rate()
360 	if (pll_con0 & BIT(pll->enable_offs)) {  in samsung_pll36xx_set_rate()
363 			tmp = readl_relaxed(pll->con_reg);  in samsung_pll36xx_set_rate()
364 		} while (!(tmp & BIT(pll->lock_offs)));  in samsung_pll36xx_set_rate()
403 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll45xx_recalc_rate()  local
407 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll45xx_recalc_rate()
412 	if (pll->type == pll_4508)  in samsung_pll45xx_recalc_rate()
437 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll45xx_set_rate()  local
443 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll45xx_set_rate()
445 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll45xx_set_rate()
450 	con0 = readl_relaxed(pll->con_reg);  in samsung_pll45xx_set_rate()
451 	con1 = readl_relaxed(pll->con_reg + 0x4);  in samsung_pll45xx_set_rate()
457 		writel_relaxed(con0, pll->con_reg);  in samsung_pll45xx_set_rate()
462 	/* Set PLL PMS values. */  in samsung_pll45xx_set_rate()
470 	/* Set PLL AFC value. */  in samsung_pll45xx_set_rate()
471 	con1 = readl_relaxed(pll->con_reg + 0x4);  in samsung_pll45xx_set_rate()
475 	/* Set PLL lock time. */  in samsung_pll45xx_set_rate()
476 	switch (pll->type) {  in samsung_pll45xx_set_rate()
478 		writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);  in samsung_pll45xx_set_rate()
481 		writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);  in samsung_pll45xx_set_rate()
488 	writel_relaxed(con1, pll->con_reg + 0x4);  in samsung_pll45xx_set_rate()
489 	writel_relaxed(con0, pll->con_reg);  in samsung_pll45xx_set_rate()
493 	while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {  in samsung_pll45xx_set_rate()
497 			pr_err("%s: could not lock PLL %s\n",  in samsung_pll45xx_set_rate()
550 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll46xx_recalc_rate()  local
554 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll46xx_recalc_rate()
555 	pll_con1 = readl_relaxed(pll->con_reg + 4);  in samsung_pll46xx_recalc_rate()
556 	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?  in samsung_pll46xx_recalc_rate()
560 	kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :  in samsung_pll46xx_recalc_rate()
563 	shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;  in samsung_pll46xx_recalc_rate()
588 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll46xx_set_rate()  local
594 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll46xx_set_rate()
596 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll46xx_set_rate()
601 	con0 = readl_relaxed(pll->con_reg);  in samsung_pll46xx_set_rate()
602 	con1 = readl_relaxed(pll->con_reg + 0x4);  in samsung_pll46xx_set_rate()
608 		writel_relaxed(con0, pll->con_reg);  in samsung_pll46xx_set_rate()
613 	/* Set PLL lock time. */  in samsung_pll46xx_set_rate()
619 	/* Set PLL PMS and VSEL values. */  in samsung_pll46xx_set_rate()
620 	if (pll->type == pll_1460x) {  in samsung_pll46xx_set_rate()
636 	/* Set PLL K, MFR and MRR values. */  in samsung_pll46xx_set_rate()
637 	con1 = readl_relaxed(pll->con_reg + 0x4);  in samsung_pll46xx_set_rate()
645 	/* Write configuration to PLL */  in samsung_pll46xx_set_rate()
646 	writel_relaxed(lock, pll->lock_reg);  in samsung_pll46xx_set_rate()
647 	writel_relaxed(con0, pll->con_reg);  in samsung_pll46xx_set_rate()
648 	writel_relaxed(con1, pll->con_reg + 0x4);  in samsung_pll46xx_set_rate()
652 	while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {  in samsung_pll46xx_set_rate()
656 			pr_err("%s: could not lock PLL %s\n",  in samsung_pll46xx_set_rate()
693 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll6552_recalc_rate()  local
697 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll6552_recalc_rate()
698 	if (pll->type == pll_6552_s3c2416) {  in samsung_pll6552_recalc_rate()
733 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll6553_recalc_rate()  local
737 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll6553_recalc_rate()
738 	pll_con1 = readl_relaxed(pll->con_reg + 0x4);  in samsung_pll6553_recalc_rate()
756  * PLL Clock Type of S3C24XX before S3C2443
771 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_s3c2410_pll_recalc_rate()  local
775 	pll_con = readl_relaxed(pll->con_reg);  in samsung_s3c2410_pll_recalc_rate()
789 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_s3c2440_mpll_recalc_rate()  local
793 	pll_con = readl_relaxed(pll->con_reg);  in samsung_s3c2440_mpll_recalc_rate()
807 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_s3c2410_pll_set_rate()  local
812 	rate = samsung_get_pll_settings(pll, drate);  in samsung_s3c2410_pll_set_rate()
814 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_s3c2410_pll_set_rate()
819 	tmp = readl_relaxed(pll->con_reg);  in samsung_s3c2410_pll_set_rate()
821 	/* Change PLL PMS values */  in samsung_s3c2410_pll_set_rate()
828 	writel_relaxed(tmp, pll->con_reg);  in samsung_s3c2410_pll_set_rate()
838 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_s3c2410_pll_enable()  local
839 	u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);  in samsung_s3c2410_pll_enable()
847 	writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);  in samsung_s3c2410_pll_enable()
934 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2550x_recalc_rate()  local
938 	pll_stat = readl_relaxed(pll->con_reg);  in samsung_pll2550x_recalc_rate()
975 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2550xx_recalc_rate()  local
979 	pll_con = readl_relaxed(pll->con_reg);  in samsung_pll2550xx_recalc_rate()
1003 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2550xx_set_rate()  local
1008 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll2550xx_set_rate()
1010 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll2550xx_set_rate()
1015 	tmp = readl_relaxed(pll->con_reg);  in samsung_pll2550xx_set_rate()
1021 		writel_relaxed(tmp, pll->con_reg);  in samsung_pll2550xx_set_rate()
1026 	/* Set PLL lock time. */  in samsung_pll2550xx_set_rate()
1027 	writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);  in samsung_pll2550xx_set_rate()
1029 	/* Change PLL PMS values */  in samsung_pll2550xx_set_rate()
1036 	writel_relaxed(tmp, pll->con_reg);  in samsung_pll2550xx_set_rate()
1041 		tmp = readl_relaxed(pll->con_reg);  in samsung_pll2550xx_set_rate()
1080 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2650x_recalc_rate()  local
1085 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll2650x_recalc_rate()
1090 	pll_con1 = readl_relaxed(pll->con_reg + 4);  in samsung_pll2650x_recalc_rate()
1103 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2650x_set_rate()  local
1108 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll2650x_set_rate()
1110 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll2650x_set_rate()
1115 	con0 = readl_relaxed(pll->con_reg);  in samsung_pll2650x_set_rate()
1116 	con1 = readl_relaxed(pll->con_reg + 4);  in samsung_pll2650x_set_rate()
1118 	/* Set PLL lock time. */  in samsung_pll2650x_set_rate()
1119 	writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);  in samsung_pll2650x_set_rate()
1121 	/* Change PLL PMS values */  in samsung_pll2650x_set_rate()
1129 	writel_relaxed(con0, pll->con_reg);  in samsung_pll2650x_set_rate()
1133 	writel_relaxed(con1, pll->con_reg + 4);  in samsung_pll2650x_set_rate()
1137 		con0 = readl_relaxed(pll->con_reg);  in samsung_pll2650x_set_rate()
1176 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2650xx_recalc_rate()  local
1181 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll2650xx_recalc_rate()
1182 	pll_con2 = readl_relaxed(pll->con_reg + 8);  in samsung_pll2650xx_recalc_rate()
1198 	struct samsung_clk_pll *pll = to_clk_pll(hw);  in samsung_pll2650xx_set_rate()  local
1202 	rate = samsung_get_pll_settings(pll, drate);  in samsung_pll2650xx_set_rate()
1204 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in samsung_pll2650xx_set_rate()
1209 	pll_con0 = readl_relaxed(pll->con_reg);  in samsung_pll2650xx_set_rate()
1210 	pll_con2 = readl_relaxed(pll->con_reg + 8);  in samsung_pll2650xx_set_rate()
1212 	 /* Change PLL PMS values */  in samsung_pll2650xx_set_rate()
1226 	/* Set PLL lock time. */  in samsung_pll2650xx_set_rate()
1227 	writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);  in samsung_pll2650xx_set_rate()
1229 	writel_relaxed(pll_con0, pll->con_reg);  in samsung_pll2650xx_set_rate()
1230 	writel_relaxed(pll_con2, pll->con_reg + 8);  in samsung_pll2650xx_set_rate()
1233 		tmp = readl_relaxed(pll->con_reg);  in samsung_pll2650xx_set_rate()
1253 	struct samsung_clk_pll *pll;  in _samsung_clk_register_pll()  local
1257 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in _samsung_clk_register_pll()
1258 	if (!pll) {  in _samsung_clk_register_pll()
1259 		pr_err("%s: could not allocate pll clk %s\n",  in _samsung_clk_register_pll()
1274 		pll->rate_count = len;  in _samsung_clk_register_pll()
1275 		pll->rate_table = kmemdup(pll_clk->rate_table,  in _samsung_clk_register_pll()
1276 					pll->rate_count *  in _samsung_clk_register_pll()
1279 		WARN(!pll->rate_table,  in _samsung_clk_register_pll()
1297 		pll->enable_offs = PLL35XX_ENABLE_SHIFT;  in _samsung_clk_register_pll()
1298 		pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;  in _samsung_clk_register_pll()
1299 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1309 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1317 		pll->enable_offs = PLL36XX_ENABLE_SHIFT;  in _samsung_clk_register_pll()
1318 		pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;  in _samsung_clk_register_pll()
1319 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1335 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1341 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1347 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1353 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1362 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1368 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1374 		if (!pll->rate_table)  in _samsung_clk_register_pll()
1380 		pr_warn("%s: Unknown pll type for pll clk %s\n",  in _samsung_clk_register_pll()
1384 	pll->hw.init = &init;  in _samsung_clk_register_pll()
1385 	pll->type = pll_clk->type;  in _samsung_clk_register_pll()
1386 	pll->lock_reg = base + pll_clk->lock_offset;  in _samsung_clk_register_pll()
1387 	pll->con_reg = base + pll_clk->con_offset;  in _samsung_clk_register_pll()
1389 	ret = clk_hw_register(ctx->dev, &pll->hw);  in _samsung_clk_register_pll()
1391 		pr_err("%s: failed to register pll clock %s : %d\n",  in _samsung_clk_register_pll()
1393 		kfree(pll);  in _samsung_clk_register_pll()
1397 	samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);  in _samsung_clk_register_pll()