Lines Matching +full:0 +full:x00111111
27 #define ISP_PLL_LOCK 0x0000
28 #define AUD_PLL_LOCK 0x0004
29 #define ISP_PLL_CON0 0x0100
30 #define ISP_PLL_CON1 0x0104
31 #define ISP_PLL_FREQ_DET 0x0108
32 #define AUD_PLL_CON0 0x0110
33 #define AUD_PLL_CON1 0x0114
34 #define AUD_PLL_CON2 0x0118
35 #define AUD_PLL_FREQ_DET 0x011c
36 #define MUX_SEL_TOP0 0x0200
37 #define MUX_SEL_TOP1 0x0204
38 #define MUX_SEL_TOP2 0x0208
39 #define MUX_SEL_TOP3 0x020c
40 #define MUX_SEL_TOP4 0x0210
41 #define MUX_SEL_TOP_MSCL 0x0220
42 #define MUX_SEL_TOP_CAM1 0x0224
43 #define MUX_SEL_TOP_DISP 0x0228
44 #define MUX_SEL_TOP_FSYS0 0x0230
45 #define MUX_SEL_TOP_FSYS1 0x0234
46 #define MUX_SEL_TOP_PERIC0 0x0238
47 #define MUX_SEL_TOP_PERIC1 0x023c
48 #define MUX_ENABLE_TOP0 0x0300
49 #define MUX_ENABLE_TOP1 0x0304
50 #define MUX_ENABLE_TOP2 0x0308
51 #define MUX_ENABLE_TOP3 0x030c
52 #define MUX_ENABLE_TOP4 0x0310
53 #define MUX_ENABLE_TOP_MSCL 0x0320
54 #define MUX_ENABLE_TOP_CAM1 0x0324
55 #define MUX_ENABLE_TOP_DISP 0x0328
56 #define MUX_ENABLE_TOP_FSYS0 0x0330
57 #define MUX_ENABLE_TOP_FSYS1 0x0334
58 #define MUX_ENABLE_TOP_PERIC0 0x0338
59 #define MUX_ENABLE_TOP_PERIC1 0x033c
60 #define MUX_STAT_TOP0 0x0400
61 #define MUX_STAT_TOP1 0x0404
62 #define MUX_STAT_TOP2 0x0408
63 #define MUX_STAT_TOP3 0x040c
64 #define MUX_STAT_TOP4 0x0410
65 #define MUX_STAT_TOP_MSCL 0x0420
66 #define MUX_STAT_TOP_CAM1 0x0424
67 #define MUX_STAT_TOP_FSYS0 0x0430
68 #define MUX_STAT_TOP_FSYS1 0x0434
69 #define MUX_STAT_TOP_PERIC0 0x0438
70 #define MUX_STAT_TOP_PERIC1 0x043c
71 #define DIV_TOP0 0x0600
72 #define DIV_TOP1 0x0604
73 #define DIV_TOP2 0x0608
74 #define DIV_TOP3 0x060c
75 #define DIV_TOP4 0x0610
76 #define DIV_TOP_MSCL 0x0618
77 #define DIV_TOP_CAM10 0x061c
78 #define DIV_TOP_CAM11 0x0620
79 #define DIV_TOP_FSYS0 0x062c
80 #define DIV_TOP_FSYS1 0x0630
81 #define DIV_TOP_FSYS2 0x0634
82 #define DIV_TOP_PERIC0 0x0638
83 #define DIV_TOP_PERIC1 0x063c
84 #define DIV_TOP_PERIC2 0x0640
85 #define DIV_TOP_PERIC3 0x0644
86 #define DIV_TOP_PERIC4 0x0648
87 #define DIV_TOP_PLL_FREQ_DET 0x064c
88 #define DIV_STAT_TOP0 0x0700
89 #define DIV_STAT_TOP1 0x0704
90 #define DIV_STAT_TOP2 0x0708
91 #define DIV_STAT_TOP3 0x070c
92 #define DIV_STAT_TOP4 0x0710
93 #define DIV_STAT_TOP_MSCL 0x0718
94 #define DIV_STAT_TOP_CAM10 0x071c
95 #define DIV_STAT_TOP_CAM11 0x0720
96 #define DIV_STAT_TOP_FSYS0 0x072c
97 #define DIV_STAT_TOP_FSYS1 0x0730
98 #define DIV_STAT_TOP_FSYS2 0x0734
99 #define DIV_STAT_TOP_PERIC0 0x0738
100 #define DIV_STAT_TOP_PERIC1 0x073c
101 #define DIV_STAT_TOP_PERIC2 0x0740
102 #define DIV_STAT_TOP_PERIC3 0x0744
103 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
104 #define ENABLE_ACLK_TOP 0x0800
105 #define ENABLE_SCLK_TOP 0x0a00
106 #define ENABLE_SCLK_TOP_MSCL 0x0a04
107 #define ENABLE_SCLK_TOP_CAM1 0x0a08
108 #define ENABLE_SCLK_TOP_DISP 0x0a0c
109 #define ENABLE_SCLK_TOP_FSYS 0x0a10
110 #define ENABLE_SCLK_TOP_PERIC 0x0a14
111 #define ENABLE_IP_TOP 0x0b00
112 #define ENABLE_CMU_TOP 0x0c00
113 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
180 { ENABLE_ACLK_TOP, 0x67ecffed },
182 { ENABLE_SCLK_TOP_PERIC, 0x38 },
184 { ISP_PLL_CON0, 0x85cc0502 },
186 { AUD_PLL_CON0, 0x84830202 },
237 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
241 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
242 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
243 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
245 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
246 /* XspiCLK[4:0] input clock for SPI */
247 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
248 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
249 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
250 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
251 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
253 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
261 0, 1),
271 MUX_SEL_TOP1, 0, 1),
285 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
307 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
315 MUX_SEL_TOP_MSCL, 0, 1),
329 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
347 MUX_SEL_TOP_FSYS0, 0, 1),
357 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
375 MUX_SEL_TOP_PERIC0, 0, 1),
385 MUX_SEL_TOP_PERIC1, 0, 2),
389 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
409 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
423 DIV_TOP1, 0, 3),
429 DIV_TOP2, 0, 3),
445 "mout_bus_pll_user", DIV_TOP3, 0, 3),
453 DIV_TOP4, 0, 3),
457 DIV_TOP_MSCL, 0, 4),
469 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
483 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
491 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
493 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
499 DIV_TOP_FSYS1, 0, 4),
509 DIV_TOP_FSYS2, 0, 4),
519 DIV_TOP_PERIC0, 0, 4),
525 DIV_TOP_PERIC1, 0, 4),
533 DIV_TOP_PERIC2, 0, 4),
543 DIV_TOP_PERIC3, 0, 4),
553 DIV_TOP_PERIC4, 0, 4),
559 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
562 29, CLK_IGNORE_UNUSED, 0),
565 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
568 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
571 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
574 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
577 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
580 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
583 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
586 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
589 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
598 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
607 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
610 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
613 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
616 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
619 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
622 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
625 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
627 ENABLE_ACLK_TOP, 0,
628 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
632 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
636 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
638 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
640 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
642 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
644 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
646 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
648 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
652 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
653 CLK_IGNORE_UNUSED, 0),
657 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
659 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
661 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
663 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
666 3, CLK_SET_RATE_PARENT, 0),
669 1, CLK_SET_RATE_PARENT, 0),
672 0, CLK_SET_RATE_PARENT, 0),
676 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
678 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
680 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
682 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
684 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
687 CLK_IGNORE_UNUSED, 0),
690 CLK_IGNORE_UNUSED, 0),
693 CLK_IGNORE_UNUSED, 0),
695 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
697 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
699 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
703 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
705 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
707 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
725 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
726 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
727 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
728 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
768 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
770 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
775 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
776 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
818 #define MPHY_PLL_LOCK 0x0000
819 #define MPHY_PLL_CON0 0x0100
820 #define MPHY_PLL_CON1 0x0104
821 #define MPHY_PLL_FREQ_DET 0x010c
822 #define MUX_SEL_CPIF0 0x0200
823 #define DIV_CPIF 0x0600
824 #define ENABLE_SCLK_CPIF 0x0a00
838 { ENABLE_SCLK_CPIF, 0x3ff },
840 { MPHY_PLL_CON0, 0x81c70601 },
854 0, 1),
860 0, 6),
866 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
868 ENABLE_SCLK_CPIF, 4, 0, 0),
897 #define MEM0_PLL_LOCK 0x0000
898 #define MEM1_PLL_LOCK 0x0004
899 #define BUS_PLL_LOCK 0x0008
900 #define MFC_PLL_LOCK 0x000c
901 #define MEM0_PLL_CON0 0x0100
902 #define MEM0_PLL_CON1 0x0104
903 #define MEM0_PLL_FREQ_DET 0x010c
904 #define MEM1_PLL_CON0 0x0110
905 #define MEM1_PLL_CON1 0x0114
906 #define MEM1_PLL_FREQ_DET 0x011c
907 #define BUS_PLL_CON0 0x0120
908 #define BUS_PLL_CON1 0x0124
909 #define BUS_PLL_FREQ_DET 0x012c
910 #define MFC_PLL_CON0 0x0130
911 #define MFC_PLL_CON1 0x0134
912 #define MFC_PLL_FREQ_DET 0x013c
913 #define MUX_SEL_MIF0 0x0200
914 #define MUX_SEL_MIF1 0x0204
915 #define MUX_SEL_MIF2 0x0208
916 #define MUX_SEL_MIF3 0x020c
917 #define MUX_SEL_MIF4 0x0210
918 #define MUX_SEL_MIF5 0x0214
919 #define MUX_SEL_MIF6 0x0218
920 #define MUX_SEL_MIF7 0x021c
921 #define MUX_ENABLE_MIF0 0x0300
922 #define MUX_ENABLE_MIF1 0x0304
923 #define MUX_ENABLE_MIF2 0x0308
924 #define MUX_ENABLE_MIF3 0x030c
925 #define MUX_ENABLE_MIF4 0x0310
926 #define MUX_ENABLE_MIF5 0x0314
927 #define MUX_ENABLE_MIF6 0x0318
928 #define MUX_ENABLE_MIF7 0x031c
929 #define MUX_STAT_MIF0 0x0400
930 #define MUX_STAT_MIF1 0x0404
931 #define MUX_STAT_MIF2 0x0408
932 #define MUX_STAT_MIF3 0x040c
933 #define MUX_STAT_MIF4 0x0410
934 #define MUX_STAT_MIF5 0x0414
935 #define MUX_STAT_MIF6 0x0418
936 #define MUX_STAT_MIF7 0x041c
937 #define DIV_MIF1 0x0604
938 #define DIV_MIF2 0x0608
939 #define DIV_MIF3 0x060c
940 #define DIV_MIF4 0x0610
941 #define DIV_MIF5 0x0614
942 #define DIV_MIF_PLL_FREQ_DET 0x0618
943 #define DIV_STAT_MIF1 0x0704
944 #define DIV_STAT_MIF2 0x0708
945 #define DIV_STAT_MIF3 0x070c
946 #define DIV_STAT_MIF4 0x0710
947 #define DIV_STAT_MIF5 0x0714
948 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
949 #define ENABLE_ACLK_MIF0 0x0800
950 #define ENABLE_ACLK_MIF1 0x0804
951 #define ENABLE_ACLK_MIF2 0x0808
952 #define ENABLE_ACLK_MIF3 0x080c
953 #define ENABLE_PCLK_MIF 0x0900
954 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
955 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
956 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
957 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
958 #define ENABLE_SCLK_MIF 0x0a00
959 #define ENABLE_IP_MIF0 0x0b00
960 #define ENABLE_IP_MIF1 0x0b04
961 #define ENABLE_IP_MIF2 0x0b08
962 #define ENABLE_IP_MIF3 0x0b0c
963 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
964 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
965 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
966 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
967 #define CLKOUT_CMU_MIF 0x0c00
968 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
969 #define DREX_FREQ_CTRL0 0x1000
970 #define DREX_FREQ_CTRL1 0x1004
971 #define PAUSE 0x1008
972 #define DDRPHY_LOCK_CTRL 0x100c
1102 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1103 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1104 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1105 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1125 0, 1),
1145 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1151 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1165 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1179 MUX_SEL_MIF5, 0, 1),
1187 MUX_SEL_MIF6, 0, 1),
1201 MUX_SEL_MIF7, 0, 1),
1227 DIV_MIF2, 0, 3),
1235 DIV_MIF3, 0, 3),
1251 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1255 0, 3),
1261 19, CLK_IGNORE_UNUSED, 0),
1263 18, CLK_IGNORE_UNUSED, 0),
1265 17, CLK_IGNORE_UNUSED, 0),
1267 16, CLK_IGNORE_UNUSED, 0),
1269 15, CLK_IGNORE_UNUSED, 0),
1271 14, CLK_IGNORE_UNUSED, 0),
1273 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1275 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1277 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1279 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1281 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1283 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1285 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1287 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1289 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1291 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1293 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1295 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1297 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1299 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1304 CLK_IGNORE_UNUSED, 0),
1307 27, CLK_IGNORE_UNUSED, 0),
1310 26, CLK_IGNORE_UNUSED, 0),
1313 25, CLK_IGNORE_UNUSED, 0),
1316 24, CLK_IGNORE_UNUSED, 0),
1319 23, CLK_IGNORE_UNUSED, 0),
1322 22, CLK_IGNORE_UNUSED, 0),
1325 21, CLK_IGNORE_UNUSED, 0),
1328 20, CLK_IGNORE_UNUSED, 0),
1331 19, CLK_IGNORE_UNUSED, 0),
1334 18, CLK_IGNORE_UNUSED, 0),
1337 17, CLK_IGNORE_UNUSED, 0),
1340 16, CLK_IGNORE_UNUSED, 0),
1343 15, CLK_IGNORE_UNUSED, 0),
1346 14, CLK_IGNORE_UNUSED, 0),
1349 13, CLK_IGNORE_UNUSED, 0),
1352 12, CLK_IGNORE_UNUSED, 0),
1355 11, CLK_IGNORE_UNUSED, 0),
1358 10, CLK_IGNORE_UNUSED, 0),
1360 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1362 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1364 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1366 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1368 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1370 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1372 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1374 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1376 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1378 0, CLK_IGNORE_UNUSED, 0),
1382 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1384 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1386 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1388 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1390 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1392 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1394 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1397 CLK_IGNORE_UNUSED, 0),
1400 5, CLK_IGNORE_UNUSED, 0),
1402 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1405 3, CLK_IGNORE_UNUSED, 0),
1407 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1412 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1415 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1417 ENABLE_ACLK_MIF3, 0,
1418 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1422 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1424 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1426 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1428 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1430 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1432 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1435 CLK_IGNORE_UNUSED, 0),
1437 ENABLE_PCLK_MIF, 19, 0, 0),
1439 ENABLE_PCLK_MIF, 18, 0, 0),
1441 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1443 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1445 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1447 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1449 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1451 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1453 ENABLE_PCLK_MIF, 11, 0, 0),
1455 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1457 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1459 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1461 ENABLE_PCLK_MIF, 7, 0, 0),
1463 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1465 ENABLE_PCLK_MIF, 5, 0, 0),
1467 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1469 ENABLE_PCLK_MIF, 2, 0, 0),
1471 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1475 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1476 CLK_IGNORE_UNUSED, 0),
1480 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1481 CLK_IGNORE_UNUSED, 0),
1485 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1489 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1493 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1496 14, CLK_IGNORE_UNUSED, 0),
1498 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1500 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1503 7, CLK_IGNORE_UNUSED, 0),
1506 6, CLK_IGNORE_UNUSED, 0),
1509 5, CLK_IGNORE_UNUSED, 0),
1512 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1514 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1516 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1518 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1520 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1549 #define DIV_PERIC 0x0600
1550 #define DIV_STAT_PERIC 0x0700
1551 #define ENABLE_ACLK_PERIC 0x0800
1552 #define ENABLE_PCLK_PERIC0 0x0900
1553 #define ENABLE_PCLK_PERIC1 0x0904
1554 #define ENABLE_SCLK_PERIC 0x0A00
1555 #define ENABLE_IP_PERIC0 0x0B00
1556 #define ENABLE_IP_PERIC1 0x0B04
1557 #define ENABLE_IP_PERIC2 0x0B08
1571 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1572 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1573 /* sclk: uart2-0 */
1574 { ENABLE_SCLK_PERIC, 0x7 },
1580 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1586 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1588 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1590 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1592 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1596 31, CLK_SET_RATE_PARENT, 0),
1598 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1600 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1602 28, CLK_SET_RATE_PARENT, 0),
1604 26, CLK_SET_RATE_PARENT, 0),
1606 25, CLK_SET_RATE_PARENT, 0),
1608 24, CLK_SET_RATE_PARENT, 0),
1610 23, CLK_SET_RATE_PARENT, 0),
1612 22, CLK_SET_RATE_PARENT, 0),
1614 21, CLK_SET_RATE_PARENT, 0),
1616 20, CLK_SET_RATE_PARENT, 0),
1618 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1620 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1622 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1624 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1629 14, CLK_SET_RATE_PARENT, 0),
1631 13, CLK_SET_RATE_PARENT, 0),
1633 12, CLK_SET_RATE_PARENT, 0),
1635 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1637 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1639 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1641 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1643 7, CLK_SET_RATE_PARENT, 0),
1645 6, CLK_SET_RATE_PARENT, 0),
1647 5, CLK_SET_RATE_PARENT, 0),
1649 4, CLK_SET_RATE_PARENT, 0),
1651 3, CLK_SET_RATE_PARENT, 0),
1653 2, CLK_SET_RATE_PARENT, 0),
1655 1, CLK_SET_RATE_PARENT, 0),
1657 0, CLK_SET_RATE_PARENT, 0),
1661 9, CLK_SET_RATE_PARENT, 0),
1663 8, CLK_SET_RATE_PARENT, 0),
1665 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1667 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1669 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1671 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1673 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1675 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1677 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1679 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1683 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1685 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1687 19, CLK_SET_RATE_PARENT, 0),
1689 18, CLK_SET_RATE_PARENT, 0),
1691 17, 0, 0),
1693 16, 0, 0),
1694 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1696 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1698 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1700 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1703 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1705 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1707 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1710 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1712 5, CLK_SET_RATE_PARENT, 0),
1714 4, CLK_SET_RATE_PARENT, 0),
1716 3, CLK_SET_RATE_PARENT, 0),
1719 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1722 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1724 ENABLE_SCLK_PERIC, 0,
1725 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1751 #define ENABLE_ACLK_PERIS 0x0800
1752 #define ENABLE_PCLK_PERIS 0x0900
1753 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1754 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1755 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1756 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1757 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1758 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1759 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1760 #define ENABLE_SCLK_PERIS 0x0a00
1761 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1762 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1763 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1764 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1765 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1766 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1767 #define ENABLE_IP_PERIS0 0x0b00
1768 #define ENABLE_IP_PERIS1 0x0b04
1769 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1770 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1771 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1772 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1773 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1774 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1775 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1808 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1810 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1812 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1816 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1818 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1820 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1822 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1824 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1826 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1828 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1830 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1832 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1834 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1838 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1840 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1842 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1844 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1846 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1848 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1850 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1852 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1854 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1856 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1858 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1860 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1862 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1866 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1870 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1874 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1879 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1884 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1889 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1893 ENABLE_SCLK_PERIS, 10, 0, 0),
1895 ENABLE_SCLK_PERIS, 4, 0, 0),
1897 ENABLE_SCLK_PERIS, 3, 0, 0),
1901 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1905 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1909 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1913 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1917 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1921 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1943 #define MUX_SEL_FSYS0 0x0200
1944 #define MUX_SEL_FSYS1 0x0204
1945 #define MUX_SEL_FSYS2 0x0208
1946 #define MUX_SEL_FSYS3 0x020c
1947 #define MUX_SEL_FSYS4 0x0210
1948 #define MUX_ENABLE_FSYS0 0x0300
1949 #define MUX_ENABLE_FSYS1 0x0304
1950 #define MUX_ENABLE_FSYS2 0x0308
1951 #define MUX_ENABLE_FSYS3 0x030c
1952 #define MUX_ENABLE_FSYS4 0x0310
1953 #define MUX_STAT_FSYS0 0x0400
1954 #define MUX_STAT_FSYS1 0x0404
1955 #define MUX_STAT_FSYS2 0x0408
1956 #define MUX_STAT_FSYS3 0x040c
1957 #define MUX_STAT_FSYS4 0x0410
1958 #define MUX_IGNORE_FSYS2 0x0508
1959 #define MUX_IGNORE_FSYS3 0x050c
1960 #define ENABLE_ACLK_FSYS0 0x0800
1961 #define ENABLE_ACLK_FSYS1 0x0804
1962 #define ENABLE_PCLK_FSYS 0x0900
1963 #define ENABLE_SCLK_FSYS 0x0a00
1964 #define ENABLE_IP_FSYS0 0x0b00
1965 #define ENABLE_IP_FSYS1 0x0b04
2030 { MUX_SEL_FSYS0, 0 },
2031 { MUX_SEL_FSYS1, 0 },
2032 { MUX_SEL_FSYS2, 0 },
2033 { MUX_SEL_FSYS3, 0 },
2034 { MUX_SEL_FSYS4, 0 },
2041 0, 60000000),
2044 0, 125000000),
2048 0, 60000000),
2051 0, 125000000),
2054 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2056 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2059 0, 48000000),
2061 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2065 NULL, 0, 300000000),
2067 NULL, 0, 300000000),
2069 NULL, 0, 300000000),
2071 NULL, 0, 300000000),
2074 NULL, 0, 26000000),
2082 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2098 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2132 MUX_SEL_FSYS2, 0, 1),
2154 MUX_SEL_FSYS3, 0, 1),
2158 MUX_SEL_FSYS4, 0, 1),
2164 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2166 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2168 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2170 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2172 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2174 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2176 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2178 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2180 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2182 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2184 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2188 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2191 26, CLK_IGNORE_UNUSED, 0),
2193 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2195 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2198 22, CLK_IGNORE_UNUSED, 0),
2200 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2202 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2205 13, 0, 0),
2208 12, 0, 0),
2211 11, CLK_IGNORE_UNUSED, 0),
2214 10, CLK_IGNORE_UNUSED, 0),
2217 9, CLK_IGNORE_UNUSED, 0),
2220 8, CLK_IGNORE_UNUSED, 0),
2223 7, CLK_IGNORE_UNUSED, 0),
2226 6, CLK_IGNORE_UNUSED, 0),
2228 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2230 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2232 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2234 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2236 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2238 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2242 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2244 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2246 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2248 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2250 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2252 ENABLE_PCLK_FSYS, 5, 0, 0),
2254 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2256 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2258 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2260 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2263 0, CLK_IGNORE_UNUSED, 0),
2267 ENABLE_SCLK_FSYS, 21, 0, 0),
2271 ENABLE_SCLK_FSYS, 18, 0, 0),
2275 ENABLE_SCLK_FSYS, 17, 0, 0),
2278 16, 0, 0),
2281 15, 0, 0),
2284 14, 0, 0),
2287 13, 0, 0),
2290 12, 0, 0),
2294 ENABLE_SCLK_FSYS, 11, 0, 0),
2298 ENABLE_SCLK_FSYS, 10, 0, 0),
2302 ENABLE_SCLK_FSYS, 9, 0, 0),
2306 ENABLE_SCLK_FSYS, 8, 0, 0),
2310 ENABLE_SCLK_FSYS, 7, 0, 0),
2312 ENABLE_SCLK_FSYS, 6, 0, 0),
2314 ENABLE_SCLK_FSYS, 5, 0, 0),
2316 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2318 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2320 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2322 ENABLE_SCLK_FSYS, 1, 0, 0),
2324 ENABLE_SCLK_FSYS, 0, 0, 0),
2327 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2328 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2329 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2350 #define MUX_SEL_G2D0 0x0200
2351 #define MUX_SEL_ENABLE_G2D0 0x0300
2352 #define MUX_SEL_STAT_G2D0 0x0400
2353 #define DIV_G2D 0x0600
2354 #define DIV_STAT_G2D 0x0700
2355 #define DIV_ENABLE_ACLK_G2D 0x0800
2356 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2357 #define DIV_ENABLE_PCLK_G2D 0x0900
2358 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2359 #define DIV_ENABLE_IP_G2D0 0x0b00
2360 #define DIV_ENABLE_IP_G2D1 0x0b04
2361 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2377 { MUX_SEL_G2D0, 0 },
2389 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2395 DIV_G2D, 0, 2),
2401 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2403 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2405 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2407 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2409 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2412 7, 0, 0),
2414 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2416 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2418 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2420 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2422 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2424 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2426 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2430 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2434 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2436 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2438 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2440 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2442 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2444 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2446 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2448 0, 0, 0),
2452 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2473 #define DISP_PLL_LOCK 0x0000
2474 #define DISP_PLL_CON0 0x0100
2475 #define DISP_PLL_CON1 0x0104
2476 #define DISP_PLL_FREQ_DET 0x0108
2477 #define MUX_SEL_DISP0 0x0200
2478 #define MUX_SEL_DISP1 0x0204
2479 #define MUX_SEL_DISP2 0x0208
2480 #define MUX_SEL_DISP3 0x020c
2481 #define MUX_SEL_DISP4 0x0210
2482 #define MUX_ENABLE_DISP0 0x0300
2483 #define MUX_ENABLE_DISP1 0x0304
2484 #define MUX_ENABLE_DISP2 0x0308
2485 #define MUX_ENABLE_DISP3 0x030c
2486 #define MUX_ENABLE_DISP4 0x0310
2487 #define MUX_STAT_DISP0 0x0400
2488 #define MUX_STAT_DISP1 0x0404
2489 #define MUX_STAT_DISP2 0x0408
2490 #define MUX_STAT_DISP3 0x040c
2491 #define MUX_STAT_DISP4 0x0410
2492 #define MUX_IGNORE_DISP2 0x0508
2493 #define DIV_DISP 0x0600
2494 #define DIV_DISP_PLL_FREQ_DET 0x0604
2495 #define DIV_STAT_DISP 0x0700
2496 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2497 #define ENABLE_ACLK_DISP0 0x0800
2498 #define ENABLE_ACLK_DISP1 0x0804
2499 #define ENABLE_PCLK_DISP 0x0900
2500 #define ENABLE_SCLK_DISP 0x0a00
2501 #define ENABLE_IP_DISP0 0x0b00
2502 #define ENABLE_IP_DISP1 0x0b04
2503 #define CLKOUT_CMU_DISP 0x0c00
2504 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2536 { DISP_PLL_CON0, 0x85f40502 },
2538 { MUX_IGNORE_DISP2, 0x00111111 },
2539 { MUX_SEL_DISP0, 0 },
2540 { MUX_SEL_DISP1, 0 },
2541 { MUX_SEL_DISP2, 0 },
2542 { MUX_SEL_DISP3, 0 },
2543 { MUX_SEL_DISP4, 0 },
2603 1, 2, 0),
2605 1, 2, 0),
2610 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2611 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2614 NULL, 0, 188000000),
2616 NULL, 0, 100000000),
2619 NULL, 0, 300000000),
2621 NULL, 0, 166000000),
2627 0, 1),
2645 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2671 0, 1),
2681 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2696 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2714 DIV_DISP, 0, 2),
2720 ENABLE_ACLK_DISP0, 2, 0, 0),
2722 ENABLE_ACLK_DISP0, 0, 0, 0),
2726 ENABLE_ACLK_DISP1, 25, 0, 0),
2728 ENABLE_ACLK_DISP1, 24, 0, 0),
2730 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2732 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2734 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2736 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2738 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2740 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2742 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2744 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2746 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2748 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2750 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2753 12, CLK_IGNORE_UNUSED, 0),
2756 11, CLK_IGNORE_UNUSED, 0),
2759 10, CLK_IGNORE_UNUSED, 0),
2761 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2763 ENABLE_ACLK_DISP1, 7, 0, 0),
2765 ENABLE_ACLK_DISP1, 6, 0, 0),
2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2769 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2771 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2773 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2776 CLK_IGNORE_UNUSED, 0),
2779 0, CLK_IGNORE_UNUSED, 0),
2783 ENABLE_PCLK_DISP, 23, 0, 0),
2785 ENABLE_PCLK_DISP, 22, 0, 0),
2787 ENABLE_PCLK_DISP, 21, 0, 0),
2789 ENABLE_PCLK_DISP, 20, 0, 0),
2791 ENABLE_PCLK_DISP, 19, 0, 0),
2793 ENABLE_PCLK_DISP, 18, 0, 0),
2795 ENABLE_PCLK_DISP, 17, 0, 0),
2797 ENABLE_PCLK_DISP, 16, 0, 0),
2799 ENABLE_PCLK_DISP, 15, 0, 0),
2801 ENABLE_PCLK_DISP, 14, 0, 0),
2803 ENABLE_PCLK_DISP, 13, 0, 0),
2805 ENABLE_PCLK_DISP, 12, 0, 0),
2807 ENABLE_PCLK_DISP, 11, 0, 0),
2809 ENABLE_PCLK_DISP, 10, 0, 0),
2811 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2813 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2815 ENABLE_PCLK_DISP, 7, 0, 0),
2817 ENABLE_PCLK_DISP, 6, 0, 0),
2819 ENABLE_PCLK_DISP, 5, 0, 0),
2821 ENABLE_PCLK_DISP, 3, 0, 0),
2823 ENABLE_PCLK_DISP, 2, 0, 0),
2825 ENABLE_PCLK_DISP, 1, 0, 0),
2827 ENABLE_PCLK_DISP, 0, 0, 0),
2832 ENABLE_SCLK_DISP, 26, 0, 0),
2835 ENABLE_SCLK_DISP, 25, 0, 0),
2837 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2839 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2841 ENABLE_SCLK_DISP, 22, 0, 0),
2844 ENABLE_SCLK_DISP, 21, 0, 0),
2847 ENABLE_SCLK_DISP, 15, 0, 0),
2850 ENABLE_SCLK_DISP, 14, 0, 0),
2853 ENABLE_SCLK_DISP, 13, 0, 0),
2855 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2857 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2859 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2861 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2863 ENABLE_SCLK_DISP, 7, 0, 0),
2865 ENABLE_SCLK_DISP, 6, 0, 0),
2867 ENABLE_SCLK_DISP, 5, 0, 0),
2870 ENABLE_SCLK_DISP, 4, 0, 0),
2872 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2874 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2901 #define MUX_SEL_AUD0 0x0200
2902 #define MUX_SEL_AUD1 0x0204
2903 #define MUX_ENABLE_AUD0 0x0300
2904 #define MUX_ENABLE_AUD1 0x0304
2905 #define MUX_STAT_AUD0 0x0400
2906 #define DIV_AUD0 0x0600
2907 #define DIV_AUD1 0x0604
2908 #define DIV_STAT_AUD0 0x0700
2909 #define DIV_STAT_AUD1 0x0704
2910 #define ENABLE_ACLK_AUD 0x0800
2911 #define ENABLE_PCLK_AUD 0x0900
2912 #define ENABLE_SCLK_AUD0 0x0a00
2913 #define ENABLE_SCLK_AUD1 0x0a04
2914 #define ENABLE_IP_AUD0 0x0b00
2915 #define ENABLE_IP_AUD1 0x0b04
2933 { MUX_SEL_AUD0, 0 },
2934 { MUX_SEL_AUD1, 0 },
2942 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2943 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2944 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2950 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2956 MUX_SEL_AUD1, 0, 1),
2968 0, 4),
2978 DIV_AUD1, 0, 4),
2984 ENABLE_ACLK_AUD, 12, 0, 0),
2986 ENABLE_ACLK_AUD, 7, 0, 0),
2988 ENABLE_ACLK_AUD, 0, 4, 0),
2990 ENABLE_ACLK_AUD, 0, 3, 0),
2992 ENABLE_ACLK_AUD, 0, 2, 0),
2994 0, 1, 0),
2996 0, CLK_IGNORE_UNUSED, 0),
3000 13, 0, 0),
3002 12, 0, 0),
3004 11, 0, 0),
3006 ENABLE_PCLK_AUD, 10, 0, 0),
3008 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3010 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3012 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3014 ENABLE_PCLK_AUD, 6, 0, 0),
3016 ENABLE_PCLK_AUD, 5, 0, 0),
3018 ENABLE_PCLK_AUD, 4, 0, 0),
3020 ENABLE_PCLK_AUD, 3, 0, 0),
3022 2, 0, 0),
3024 ENABLE_PCLK_AUD, 0, 0, 0),
3028 2, CLK_IGNORE_UNUSED, 0),
3030 ENABLE_SCLK_AUD0, 1, 0, 0),
3032 0, 0, 0),
3036 ENABLE_SCLK_AUD1, 6, 0, 0),
3038 ENABLE_SCLK_AUD1, 5, 0, 0),
3040 ENABLE_SCLK_AUD1, 4, 0, 0),
3042 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3044 ENABLE_SCLK_AUD1, 2, 0, 0),
3046 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3048 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3069 * Register offset definitions for CMU_BUS{0|1|2}
3071 #define DIV_BUS 0x0600
3072 #define DIV_STAT_BUS 0x0700
3073 #define ENABLE_ACLK_BUS 0x0800
3074 #define ENABLE_PCLK_BUS 0x0900
3075 #define ENABLE_IP_BUS0 0x0b00
3076 #define ENABLE_IP_BUS1 0x0b04
3078 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3079 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3080 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3105 DIV_BUS, 0, 3),
3112 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3114 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3116 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3120 ENABLE_PCLK_BUS, 2, 0, 0),
3122 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3124 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3131 DIV_BUS, 0, 3),
3137 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3139 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3141 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3145 ENABLE_PCLK_BUS, 2, 0, 0),
3147 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3149 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3156 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3162 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3168 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3170 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3173 1, CLK_IGNORE_UNUSED, 0),
3176 0, CLK_IGNORE_UNUSED, 0),
3180 ENABLE_PCLK_BUS, 2, 0, 0),
3182 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3184 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3195 CMU_BUS_INFO_CLKS(0),
3223 exynos5433_cmu_bus_init(0);
3230 #define G3D_PLL_LOCK 0x0000
3231 #define G3D_PLL_CON0 0x0100
3232 #define G3D_PLL_CON1 0x0104
3233 #define G3D_PLL_FREQ_DET 0x010c
3234 #define MUX_SEL_G3D 0x0200
3235 #define MUX_ENABLE_G3D 0x0300
3236 #define MUX_STAT_G3D 0x0400
3237 #define DIV_G3D 0x0600
3238 #define DIV_G3D_PLL_FREQ_DET 0x0604
3239 #define DIV_STAT_G3D 0x0700
3240 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3241 #define ENABLE_ACLK_G3D 0x0800
3242 #define ENABLE_PCLK_G3D 0x0900
3243 #define ENABLE_SCLK_G3D 0x0a00
3244 #define ENABLE_IP_G3D0 0x0b00
3245 #define ENABLE_IP_G3D1 0x0b04
3246 #define CLKOUT_CMU_G3D 0x0c00
3247 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3248 #define CLK_STOPCTRL 0x1000
3270 { MUX_SEL_G3D, 0 },
3285 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3287 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3297 0, 3, CLK_SET_RATE_PARENT, 0),
3303 ENABLE_ACLK_G3D, 7, 0, 0),
3305 ENABLE_ACLK_G3D, 6, 0, 0),
3307 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3309 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3311 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3313 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3315 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3317 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3321 ENABLE_PCLK_G3D, 3, 0, 0),
3323 ENABLE_PCLK_G3D, 2, 0, 0),
3325 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3327 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3331 ENABLE_SCLK_G3D, 0, 0, 0),
3354 #define MUX_SEL_GSCL 0x0200
3355 #define MUX_ENABLE_GSCL 0x0300
3356 #define MUX_STAT_GSCL 0x0400
3357 #define ENABLE_ACLK_GSCL 0x0800
3358 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3359 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3360 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3361 #define ENABLE_PCLK_GSCL 0x0900
3362 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3363 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3364 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3365 #define ENABLE_IP_GSCL0 0x0b00
3366 #define ENABLE_IP_GSCL1 0x0b04
3367 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3368 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3369 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3390 { MUX_SEL_GSCL, 0 },
3391 { ENABLE_ACLK_GSCL, 0xfff },
3392 { ENABLE_PCLK_GSCL, 0xff },
3404 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3410 ENABLE_ACLK_GSCL, 11, 0, 0),
3412 ENABLE_ACLK_GSCL, 10, 0, 0),
3414 ENABLE_ACLK_GSCL, 9, 0, 0),
3417 8, CLK_IGNORE_UNUSED, 0),
3419 ENABLE_ACLK_GSCL, 7, 0, 0),
3421 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3424 CLK_IGNORE_UNUSED, 0),
3427 CLK_IGNORE_UNUSED, 0),
3429 ENABLE_ACLK_GSCL, 3, 0, 0),
3431 ENABLE_ACLK_GSCL, 2, 0, 0),
3433 ENABLE_ACLK_GSCL, 1, 0, 0),
3435 ENABLE_ACLK_GSCL, 0, 0, 0),
3439 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3443 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3447 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3451 ENABLE_PCLK_GSCL, 7, 0, 0),
3453 ENABLE_PCLK_GSCL, 6, 0, 0),
3455 ENABLE_PCLK_GSCL, 5, 0, 0),
3457 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3460 3, CLK_IGNORE_UNUSED, 0),
3462 ENABLE_PCLK_GSCL, 2, 0, 0),
3464 ENABLE_PCLK_GSCL, 1, 0, 0),
3466 ENABLE_PCLK_GSCL, 0, 0, 0),
3470 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3474 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3478 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3497 #define APOLLO_PLL_LOCK 0x0000
3498 #define APOLLO_PLL_CON0 0x0100
3499 #define APOLLO_PLL_CON1 0x0104
3500 #define APOLLO_PLL_FREQ_DET 0x010c
3501 #define MUX_SEL_APOLLO0 0x0200
3502 #define MUX_SEL_APOLLO1 0x0204
3503 #define MUX_SEL_APOLLO2 0x0208
3504 #define MUX_ENABLE_APOLLO0 0x0300
3505 #define MUX_ENABLE_APOLLO1 0x0304
3506 #define MUX_ENABLE_APOLLO2 0x0308
3507 #define MUX_STAT_APOLLO0 0x0400
3508 #define MUX_STAT_APOLLO1 0x0404
3509 #define MUX_STAT_APOLLO2 0x0408
3510 #define DIV_APOLLO0 0x0600
3511 #define DIV_APOLLO1 0x0604
3512 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3513 #define DIV_STAT_APOLLO0 0x0700
3514 #define DIV_STAT_APOLLO1 0x0704
3515 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3516 #define ENABLE_ACLK_APOLLO 0x0800
3517 #define ENABLE_PCLK_APOLLO 0x0900
3518 #define ENABLE_SCLK_APOLLO 0x0a00
3519 #define ENABLE_IP_APOLLO0 0x0b00
3520 #define ENABLE_IP_APOLLO1 0x0b04
3521 #define CLKOUT_CMU_APOLLO 0x0c00
3522 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3523 #define ARMCLK_STOPCTRL 0x1000
3524 #define APOLLO_PWR_CTRL 0x1020
3525 #define APOLLO_PWR_CTRL2 0x1024
3526 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3527 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3528 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3573 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3574 CLK_RECALC_NEW_RATES, 0),
3578 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3582 0, 1, CLK_SET_RATE_PARENT, 0),
3603 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3605 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3612 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3620 6, CLK_IGNORE_UNUSED, 0),
3623 5, CLK_IGNORE_UNUSED, 0),
3626 4, CLK_IGNORE_UNUSED, 0),
3629 3, CLK_IGNORE_UNUSED, 0),
3632 2, CLK_IGNORE_UNUSED, 0),
3635 1, CLK_IGNORE_UNUSED, 0),
3638 0, CLK_IGNORE_UNUSED, 0),
3643 2, CLK_IGNORE_UNUSED, 0),
3645 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3648 0, CLK_IGNORE_UNUSED, 0),
3652 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3654 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3662 (((hpm) << 4) | ((copy) << 0))
3675 { 0 },
3684 reg_base = of_iomap(np, 0); in exynos5433_cmu_apollo_init()
3708 hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200, in exynos5433_cmu_apollo_init()
3723 #define ATLAS_PLL_LOCK 0x0000
3724 #define ATLAS_PLL_CON0 0x0100
3725 #define ATLAS_PLL_CON1 0x0104
3726 #define ATLAS_PLL_FREQ_DET 0x010c
3727 #define MUX_SEL_ATLAS0 0x0200
3728 #define MUX_SEL_ATLAS1 0x0204
3729 #define MUX_SEL_ATLAS2 0x0208
3730 #define MUX_ENABLE_ATLAS0 0x0300
3731 #define MUX_ENABLE_ATLAS1 0x0304
3732 #define MUX_ENABLE_ATLAS2 0x0308
3733 #define MUX_STAT_ATLAS0 0x0400
3734 #define MUX_STAT_ATLAS1 0x0404
3735 #define MUX_STAT_ATLAS2 0x0408
3736 #define DIV_ATLAS0 0x0600
3737 #define DIV_ATLAS1 0x0604
3738 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3739 #define DIV_STAT_ATLAS0 0x0700
3740 #define DIV_STAT_ATLAS1 0x0704
3741 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3742 #define ENABLE_ACLK_ATLAS 0x0800
3743 #define ENABLE_PCLK_ATLAS 0x0900
3744 #define ENABLE_SCLK_ATLAS 0x0a00
3745 #define ENABLE_IP_ATLAS0 0x0b00
3746 #define ENABLE_IP_ATLAS1 0x0b04
3747 #define CLKOUT_CMU_ATLAS 0x0c00
3748 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3749 #define ARMCLK_STOPCTRL 0x1000
3750 #define ATLAS_PWR_CTRL 0x1020
3751 #define ATLAS_PWR_CTRL2 0x1024
3752 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3753 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3754 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3799 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3800 CLK_RECALC_NEW_RATES, 0),
3804 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3808 0, 1, CLK_SET_RATE_PARENT, 0),
3829 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3831 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3838 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3846 9, CLK_IGNORE_UNUSED, 0),
3849 8, CLK_IGNORE_UNUSED, 0),
3852 7, CLK_IGNORE_UNUSED, 0),
3855 6, CLK_IGNORE_UNUSED, 0),
3858 5, CLK_IGNORE_UNUSED, 0),
3861 4, CLK_IGNORE_UNUSED, 0),
3864 3, CLK_IGNORE_UNUSED, 0),
3867 2, CLK_IGNORE_UNUSED, 0),
3869 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3871 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3876 5, CLK_IGNORE_UNUSED, 0),
3879 4, CLK_IGNORE_UNUSED, 0),
3882 3, CLK_IGNORE_UNUSED, 0),
3884 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3886 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3888 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3892 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3894 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3896 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3898 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3900 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3902 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3904 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3906 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3914 (((hpm) << 4) | ((copy) << 0))
3932 { 0 },
3941 reg_base = of_iomap(np, 0); in exynos5433_cmu_atlas_init()
3965 hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200, in exynos5433_cmu_atlas_init()
3980 #define MUX_SEL_MSCL0 0x0200
3981 #define MUX_SEL_MSCL1 0x0204
3982 #define MUX_ENABLE_MSCL0 0x0300
3983 #define MUX_ENABLE_MSCL1 0x0304
3984 #define MUX_STAT_MSCL0 0x0400
3985 #define MUX_STAT_MSCL1 0x0404
3986 #define DIV_MSCL 0x0600
3987 #define DIV_STAT_MSCL 0x0700
3988 #define ENABLE_ACLK_MSCL 0x0800
3989 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3990 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3991 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3992 #define ENABLE_PCLK_MSCL 0x0900
3993 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3994 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3995 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3996 #define ENABLE_SCLK_MSCL 0x0a00
3997 #define ENABLE_IP_MSCL0 0x0b00
3998 #define ENABLE_IP_MSCL1 0x0b04
3999 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
4000 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
4001 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
4026 { MUX_SEL_MSCL0, 0 },
4027 { MUX_SEL_MSCL1, 0 },
4041 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4045 MUX_SEL_MSCL1, 0, 1),
4051 DIV_MSCL, 0, 3),
4057 ENABLE_ACLK_MSCL, 9, 0, 0),
4059 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4061 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4063 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4065 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4067 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4069 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4071 ENABLE_ACLK_MSCL, 2, 0, 0),
4073 ENABLE_ACLK_MSCL, 1, 0, 0),
4075 ENABLE_ACLK_MSCL, 0, 0, 0),
4081 0, CLK_IGNORE_UNUSED, 0),
4087 0, CLK_IGNORE_UNUSED, 0),
4092 0, CLK_IGNORE_UNUSED, 0),
4096 ENABLE_PCLK_MSCL, 7, 0, 0),
4098 ENABLE_PCLK_MSCL, 6, 0, 0),
4100 ENABLE_PCLK_MSCL, 5, 0, 0),
4102 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4104 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4106 ENABLE_PCLK_MSCL, 2, 0, 0),
4108 ENABLE_PCLK_MSCL, 1, 0, 0),
4110 ENABLE_PCLK_MSCL, 0, 0, 0),
4115 0, CLK_IGNORE_UNUSED, 0),
4120 0, CLK_IGNORE_UNUSED, 0),
4125 0, CLK_IGNORE_UNUSED, 0),
4128 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4129 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4150 #define MUX_SEL_MFC 0x0200
4151 #define MUX_ENABLE_MFC 0x0300
4152 #define MUX_STAT_MFC 0x0400
4153 #define DIV_MFC 0x0600
4154 #define DIV_STAT_MFC 0x0700
4155 #define ENABLE_ACLK_MFC 0x0800
4156 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4157 #define ENABLE_PCLK_MFC 0x0900
4158 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4159 #define ENABLE_IP_MFC0 0x0b00
4160 #define ENABLE_IP_MFC1 0x0b04
4161 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4177 { MUX_SEL_MFC, 0 },
4185 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4191 DIV_MFC, 0, 2),
4197 ENABLE_ACLK_MFC, 6, 0, 0),
4199 ENABLE_ACLK_MFC, 5, 0, 0),
4201 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4203 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4205 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4207 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4209 ENABLE_ACLK_MFC, 0, 0, 0),
4214 1, CLK_IGNORE_UNUSED, 0),
4217 0, CLK_IGNORE_UNUSED, 0),
4221 ENABLE_PCLK_MFC, 4, 0, 0),
4223 ENABLE_PCLK_MFC, 3, 0, 0),
4225 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4227 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4229 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4234 1, CLK_IGNORE_UNUSED, 0),
4237 0, CLK_IGNORE_UNUSED, 0),
4258 #define MUX_SEL_HEVC 0x0200
4259 #define MUX_ENABLE_HEVC 0x0300
4260 #define MUX_STAT_HEVC 0x0400
4261 #define DIV_HEVC 0x0600
4262 #define DIV_STAT_HEVC 0x0700
4263 #define ENABLE_ACLK_HEVC 0x0800
4264 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4265 #define ENABLE_PCLK_HEVC 0x0900
4266 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4267 #define ENABLE_IP_HEVC0 0x0b00
4268 #define ENABLE_IP_HEVC1 0x0b04
4269 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4285 { MUX_SEL_HEVC, 0 },
4293 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4299 DIV_HEVC, 0, 2),
4305 ENABLE_ACLK_HEVC, 6, 0, 0),
4307 ENABLE_ACLK_HEVC, 5, 0, 0),
4309 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4311 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4313 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4315 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4317 ENABLE_ACLK_HEVC, 0, 0, 0),
4323 1, CLK_IGNORE_UNUSED, 0),
4327 0, CLK_IGNORE_UNUSED, 0),
4331 ENABLE_PCLK_HEVC, 4, 0, 0),
4333 ENABLE_PCLK_HEVC, 3, 0, 0),
4335 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4337 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4339 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4344 1, CLK_IGNORE_UNUSED, 0),
4347 0, CLK_IGNORE_UNUSED, 0),
4368 #define MUX_SEL_ISP 0x0200
4369 #define MUX_ENABLE_ISP 0x0300
4370 #define MUX_STAT_ISP 0x0400
4371 #define DIV_ISP 0x0600
4372 #define DIV_STAT_ISP 0x0700
4373 #define ENABLE_ACLK_ISP0 0x0800
4374 #define ENABLE_ACLK_ISP1 0x0804
4375 #define ENABLE_ACLK_ISP2 0x0808
4376 #define ENABLE_PCLK_ISP 0x0900
4377 #define ENABLE_SCLK_ISP 0x0a00
4378 #define ENABLE_IP_ISP0 0x0b00
4379 #define ENABLE_IP_ISP1 0x0b04
4380 #define ENABLE_IP_ISP2 0x0b08
4381 #define ENABLE_IP_ISP3 0x0b0c
4399 { MUX_SEL_ISP, 0 },
4408 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4410 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4422 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4428 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4430 ENABLE_ACLK_ISP0, 5, 0, 0),
4432 ENABLE_ACLK_ISP0, 4, 0, 0),
4434 ENABLE_ACLK_ISP0, 3, 0, 0),
4436 ENABLE_ACLK_ISP0, 2, 0, 0),
4438 ENABLE_ACLK_ISP0, 1, 0, 0),
4440 ENABLE_ACLK_ISP0, 0, 0, 0),
4445 17, CLK_IGNORE_UNUSED, 0),
4448 16, CLK_IGNORE_UNUSED, 0),
4451 15, CLK_IGNORE_UNUSED, 0),
4454 14, CLK_IGNORE_UNUSED, 0),
4457 13, CLK_IGNORE_UNUSED, 0),
4460 12, CLK_IGNORE_UNUSED, 0),
4463 11, CLK_IGNORE_UNUSED, 0),
4466 10, CLK_IGNORE_UNUSED, 0),
4469 9, CLK_IGNORE_UNUSED, 0),
4472 8, CLK_IGNORE_UNUSED, 0),
4475 7, CLK_IGNORE_UNUSED, 0),
4477 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4479 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4482 4, CLK_IGNORE_UNUSED, 0),
4485 3, CLK_IGNORE_UNUSED, 0),
4487 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4489 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4491 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4496 13, CLK_IGNORE_UNUSED, 0),
4498 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4500 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4502 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4505 9, CLK_IGNORE_UNUSED, 0),
4507 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4509 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4512 6, CLK_IGNORE_UNUSED, 0),
4514 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4516 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4518 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4521 2, CLK_IGNORE_UNUSED, 0),
4523 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4525 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4529 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4531 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4533 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4535 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4537 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4539 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4541 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4543 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4545 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4547 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4549 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4551 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4553 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4555 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4557 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4559 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4561 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4563 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4566 7, CLK_IGNORE_UNUSED, 0),
4568 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4570 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4572 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4574 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4576 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4578 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4580 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4585 5, CLK_IGNORE_UNUSED, 0),
4588 4, CLK_IGNORE_UNUSED, 0),
4591 3, CLK_IGNORE_UNUSED, 0),
4594 2, CLK_IGNORE_UNUSED, 0),
4597 1, CLK_IGNORE_UNUSED, 0),
4600 0, CLK_IGNORE_UNUSED, 0),
4621 #define MUX_SEL_CAM00 0x0200
4622 #define MUX_SEL_CAM01 0x0204
4623 #define MUX_SEL_CAM02 0x0208
4624 #define MUX_SEL_CAM03 0x020c
4625 #define MUX_SEL_CAM04 0x0210
4626 #define MUX_ENABLE_CAM00 0x0300
4627 #define MUX_ENABLE_CAM01 0x0304
4628 #define MUX_ENABLE_CAM02 0x0308
4629 #define MUX_ENABLE_CAM03 0x030c
4630 #define MUX_ENABLE_CAM04 0x0310
4631 #define MUX_STAT_CAM00 0x0400
4632 #define MUX_STAT_CAM01 0x0404
4633 #define MUX_STAT_CAM02 0x0408
4634 #define MUX_STAT_CAM03 0x040c
4635 #define MUX_STAT_CAM04 0x0410
4636 #define MUX_IGNORE_CAM01 0x0504
4637 #define DIV_CAM00 0x0600
4638 #define DIV_CAM01 0x0604
4639 #define DIV_CAM02 0x0608
4640 #define DIV_CAM03 0x060c
4641 #define DIV_STAT_CAM00 0x0700
4642 #define DIV_STAT_CAM01 0x0704
4643 #define DIV_STAT_CAM02 0x0708
4644 #define DIV_STAT_CAM03 0x070c
4645 #define ENABLE_ACLK_CAM00 0X0800
4646 #define ENABLE_ACLK_CAM01 0X0804
4647 #define ENABLE_ACLK_CAM02 0X0808
4648 #define ENABLE_PCLK_CAM0 0X0900
4649 #define ENABLE_SCLK_CAM0 0X0a00
4650 #define ENABLE_IP_CAM00 0X0b00
4651 #define ENABLE_IP_CAM01 0X0b04
4652 #define ENABLE_IP_CAM02 0X0b08
4653 #define ENABLE_IP_CAM03 0X0b0C
4683 { MUX_SEL_CAM00, 0 },
4684 { MUX_SEL_CAM01, 0 },
4685 { MUX_SEL_CAM02, 0 },
4686 { MUX_SEL_CAM03, 0 },
4687 { MUX_SEL_CAM04, 0 },
4750 NULL, 0, 100000000),
4752 NULL, 0, 100000000),
4762 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4772 MUX_SEL_CAM01, 0, 1),
4788 MUX_SEL_CAM02, 0, 1),
4806 MUX_SEL_CAM03, 0, 1),
4826 MUX_SEL_CAM04, 0, 1),
4836 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4850 DIV_CAM01, 0, 3),
4864 DIV_CAM02, 0, 3),
4873 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4879 6, 0, 0),
4881 5, 0, 0),
4883 4, 0, 0),
4885 3, 0, 0),
4887 ENABLE_ACLK_CAM00, 2, 0, 0),
4889 ENABLE_ACLK_CAM00, 1, 0, 0),
4891 ENABLE_ACLK_CAM00, 0, 0, 0),
4895 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4897 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4899 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4901 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4903 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4905 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4907 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4909 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4912 23, CLK_IGNORE_UNUSED, 0),
4915 22, CLK_IGNORE_UNUSED, 0),
4918 21, CLK_IGNORE_UNUSED, 0),
4921 20, CLK_IGNORE_UNUSED, 0),
4924 19, CLK_IGNORE_UNUSED, 0),
4927 18, CLK_IGNORE_UNUSED, 0),
4930 17, CLK_IGNORE_UNUSED, 0),
4933 16, CLK_IGNORE_UNUSED, 0),
4936 15, CLK_IGNORE_UNUSED, 0),
4939 14, CLK_IGNORE_UNUSED, 0),
4942 13, CLK_IGNORE_UNUSED, 0),
4945 12, CLK_IGNORE_UNUSED, 0),
4948 11, CLK_IGNORE_UNUSED, 0),
4951 10, CLK_IGNORE_UNUSED, 0),
4954 9, CLK_IGNORE_UNUSED, 0),
4957 8, CLK_IGNORE_UNUSED, 0),
4960 7, CLK_IGNORE_UNUSED, 0),
4963 6, CLK_IGNORE_UNUSED, 0),
4965 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4967 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4969 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4971 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4973 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4975 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4979 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4981 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4983 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4985 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4987 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4989 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4991 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4993 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4995 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4997 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
5001 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
5003 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
5005 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5007 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5009 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5011 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5013 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5015 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5017 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5019 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5021 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5023 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5025 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5028 12, CLK_IGNORE_UNUSED, 0),
5031 11, CLK_IGNORE_UNUSED, 0),
5034 10, CLK_IGNORE_UNUSED, 0),
5036 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5038 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5041 7, CLK_IGNORE_UNUSED, 0),
5043 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5045 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5047 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5049 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5051 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5053 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5055 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5060 ENABLE_SCLK_CAM0, 8, 0, 0),
5063 ENABLE_SCLK_CAM0, 7, 0, 0),
5065 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5067 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5069 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5071 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5074 ENABLE_SCLK_CAM0, 2, 0, 0),
5077 ENABLE_SCLK_CAM0, 1, 0, 0),
5080 ENABLE_SCLK_CAM0, 0, 0, 0),
5103 #define MUX_SEL_CAM10 0x0200
5104 #define MUX_SEL_CAM11 0x0204
5105 #define MUX_SEL_CAM12 0x0208
5106 #define MUX_ENABLE_CAM10 0x0300
5107 #define MUX_ENABLE_CAM11 0x0304
5108 #define MUX_ENABLE_CAM12 0x0308
5109 #define MUX_STAT_CAM10 0x0400
5110 #define MUX_STAT_CAM11 0x0404
5111 #define MUX_STAT_CAM12 0x0408
5112 #define MUX_IGNORE_CAM11 0x0504
5113 #define DIV_CAM10 0x0600
5114 #define DIV_CAM11 0x0604
5115 #define DIV_STAT_CAM10 0x0700
5116 #define DIV_STAT_CAM11 0x0704
5117 #define ENABLE_ACLK_CAM10 0X0800
5118 #define ENABLE_ACLK_CAM11 0X0804
5119 #define ENABLE_ACLK_CAM12 0X0808
5120 #define ENABLE_PCLK_CAM1 0X0900
5121 #define ENABLE_SCLK_CAM1 0X0a00
5122 #define ENABLE_IP_CAM10 0X0b00
5123 #define ENABLE_IP_CAM11 0X0b04
5124 #define ENABLE_IP_CAM12 0X0b08
5147 { MUX_SEL_CAM10, 0 },
5148 { MUX_SEL_CAM11, 0 },
5149 { MUX_SEL_CAM12, 0 },
5180 0, 100000000),
5196 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5202 MUX_SEL_CAM11, 0, 1),
5216 MUX_SEL_CAM12, 0, 1),
5230 DIV_CAM10, 0, 3),
5240 DIV_CAM11, 0, 3),
5246 ENABLE_ACLK_CAM10, 4, 0, 0),
5248 ENABLE_ACLK_CAM10, 3, 0, 0),
5250 ENABLE_ACLK_CAM10, 1, 0, 0),
5252 ENABLE_ACLK_CAM10, 0, 0, 0),
5256 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5258 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5261 27, CLK_IGNORE_UNUSED, 0),
5264 26, CLK_IGNORE_UNUSED, 0),
5267 25, CLK_IGNORE_UNUSED, 0),
5270 24, CLK_IGNORE_UNUSED, 0),
5273 23, CLK_IGNORE_UNUSED, 0),
5276 22, CLK_IGNORE_UNUSED, 0),
5279 21, CLK_IGNORE_UNUSED, 0),
5282 20, CLK_IGNORE_UNUSED, 0),
5285 19, CLK_IGNORE_UNUSED, 0),
5288 18, CLK_IGNORE_UNUSED, 0),
5291 17, CLK_IGNORE_UNUSED, 0),
5294 16, CLK_IGNORE_UNUSED, 0),
5297 15, CLK_IGNORE_UNUSED, 0),
5299 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5302 13, CLK_IGNORE_UNUSED, 0),
5305 12, CLK_IGNORE_UNUSED, 0),
5307 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5309 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5312 9, CLK_IGNORE_UNUSED, 0),
5314 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5316 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5318 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5320 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5322 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5324 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5326 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5328 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5330 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5335 10, CLK_IGNORE_UNUSED, 0),
5337 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5340 8, CLK_IGNORE_UNUSED, 0),
5342 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5344 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5346 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5349 4, CLK_IGNORE_UNUSED, 0),
5352 3, CLK_IGNORE_UNUSED, 0),
5355 2, CLK_IGNORE_UNUSED, 0),
5357 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5360 0, CLK_IGNORE_UNUSED, 0),
5364 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5366 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5368 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5370 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5372 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5374 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5376 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5379 20, CLK_IGNORE_UNUSED, 0),
5382 19, CLK_IGNORE_UNUSED, 0),
5384 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5387 17, CLK_IGNORE_UNUSED, 0),
5389 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5391 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5394 14, CLK_IGNORE_UNUSED, 0),
5396 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5398 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5400 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5402 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5404 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5406 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5408 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5410 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5412 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5414 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5416 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5418 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5420 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5422 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5426 15, 0, 0),
5428 14, 0, 0),
5430 13, 0, 0),
5432 12, 0, 0),
5435 ENABLE_SCLK_CAM1, 11, 0, 0),
5437 ENABLE_SCLK_CAM1, 10, 0, 0),
5439 ENABLE_SCLK_CAM1, 9, 0, 0),
5441 ENABLE_SCLK_CAM1, 7, 0, 0),
5443 ENABLE_SCLK_CAM1, 6, 0, 0),
5445 ENABLE_SCLK_CAM1, 5, 0, 0),
5447 ENABLE_SCLK_CAM1, 4, 0, 0),
5449 ENABLE_SCLK_CAM1, 3, 0, 0),
5451 ENABLE_SCLK_CAM1, 2, 0, 0),
5453 ENABLE_SCLK_CAM1, 1, 0, 0),
5455 ENABLE_SCLK_CAM1, 0, 0, 0),
5478 #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
5479 #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
5489 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5493 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5527 for (i = 0; i < data->nr_pclks; i++) in exynos5433_cmu_suspend()
5534 for (i = 0; i < data->nr_pclks; i++) in exynos5433_cmu_suspend()
5539 return 0; in exynos5433_cmu_suspend()
5549 for (i = 0; i < data->nr_pclks; i++) in exynos5433_cmu_resume()
5555 for (i = 0; i < data->nr_pclks; i++) in exynos5433_cmu_resume()
5558 return 0; in exynos5433_cmu_resume()
5580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in exynos5433_cmu_probe()
5585 for (i = 0; i < info->nr_clk_ids; ++i) in exynos5433_cmu_probe()
5602 if (data->nr_pclks > 0) { in exynos5433_cmu_probe()
5609 for (i = 0; i < data->nr_pclks; i++) { in exynos5433_cmu_probe()
5614 while (--i >= 0) in exynos5433_cmu_probe()
5660 return 0; in exynos5433_cmu_probe()