Lines Matching +full:reg +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
14 #include <dt-bindings/reset/rk628-rgu.h>
15 #include <dt-bindings/clock/rk628-cgu.h>
17 #include "clk-regmap.h"
22 #define REG(x) ((x) + 0xc0000) macro
24 #define CRU_CPLL_CON0 REG(0x0000)
25 #define CRU_CPLL_CON1 REG(0x0004)
26 #define CRU_CPLL_CON2 REG(0x0008)
27 #define CRU_CPLL_CON3 REG(0x000c)
28 #define CRU_CPLL_CON4 REG(0x0010)
29 #define CRU_GPLL_CON0 REG(0x0020)
30 #define CRU_GPLL_CON1 REG(0x0024)
31 #define CRU_GPLL_CON2 REG(0x0028)
32 #define CRU_GPLL_CON3 REG(0x002c)
33 #define CRU_GPLL_CON4 REG(0x0030)
34 #define CRU_MODE_CON REG(0x0060)
35 #define CRU_CLKSEL_CON00 REG(0x0080)
36 #define CRU_CLKSEL_CON01 REG(0x0084)
37 #define CRU_CLKSEL_CON02 REG(0x0088)
38 #define CRU_CLKSEL_CON03 REG(0x008c)
39 #define CRU_CLKSEL_CON04 REG(0x0090)
40 #define CRU_CLKSEL_CON05 REG(0x0094)
41 #define CRU_CLKSEL_CON06 REG(0x0098)
42 #define CRU_CLKSEL_CON07 REG(0x009c)
43 #define CRU_CLKSEL_CON08 REG(0x00a0)
44 #define CRU_CLKSEL_CON09 REG(0x00a4)
45 #define CRU_CLKSEL_CON10 REG(0x00a8)
46 #define CRU_CLKSEL_CON11 REG(0x00ac)
47 #define CRU_CLKSEL_CON12 REG(0x00b0)
48 #define CRU_CLKSEL_CON13 REG(0x00b4)
49 #define CRU_CLKSEL_CON14 REG(0x00b8)
50 #define CRU_CLKSEL_CON15 REG(0x00bc)
51 #define CRU_CLKSEL_CON16 REG(0x00c0)
52 #define CRU_CLKSEL_CON17 REG(0x00c4)
53 #define CRU_CLKSEL_CON18 REG(0x00c8)
54 #define CRU_CLKSEL_CON20 REG(0x00d0)
55 #define CRU_CLKSEL_CON21 REG(0x00d4)
56 #define CRU_GATE_CON00 REG(0x0180)
57 #define CRU_GATE_CON01 REG(0x0184)
58 #define CRU_GATE_CON02 REG(0x0188)
59 #define CRU_GATE_CON03 REG(0x018c)
60 #define CRU_GATE_CON04 REG(0x0190)
61 #define CRU_GATE_CON05 REG(0x0194)
62 #define CRU_SOFTRST_CON00 REG(0x0200)
63 #define CRU_SOFTRST_CON01 REG(0x0204)
64 #define CRU_SOFTRST_CON02 REG(0x0208)
65 #define CRU_SOFTRST_CON04 REG(0x0210)
269 if (cru->clk_data.clks && id) in rk628_clk_add_lookup()
270 cru->clk_data.clks[id] = clk; in rk628_clk_add_lookup()
279 const struct clk_mux_data *data = &rk628_clk_muxes[i]; in rk628_clk_register_muxes() local
281 clk = devm_clk_regmap_register_mux(cru->dev, data->name, in rk628_clk_register_muxes()
282 data->parent_names, in rk628_clk_register_muxes()
283 data->num_parents, in rk628_clk_register_muxes()
284 cru->regmap, data->reg, in rk628_clk_register_muxes()
285 data->shift, data->width, in rk628_clk_register_muxes()
286 data->flags); in rk628_clk_register_muxes()
288 dev_err(cru->dev, "failed to register clock %s\n", in rk628_clk_register_muxes()
289 data->name); in rk628_clk_register_muxes()
293 rk628_clk_add_lookup(cru, clk, data->id); in rk628_clk_register_muxes()
303 const struct clk_gate_data *data = &rk628_clk_gates[i]; in rk628_clk_register_gates() local
305 clk = devm_clk_regmap_register_gate(cru->dev, data->name, in rk628_clk_register_gates()
306 data->parent_name, in rk628_clk_register_gates()
307 cru->regmap, in rk628_clk_register_gates()
308 data->reg, data->shift, in rk628_clk_register_gates()
309 data->flags); in rk628_clk_register_gates()
311 dev_err(cru->dev, "failed to register clock %s\n", in rk628_clk_register_gates()
312 data->name); in rk628_clk_register_gates()
316 rk628_clk_add_lookup(cru, clk, data->id); in rk628_clk_register_gates()
326 const struct clk_composite_data *data = in rk628_clk_register_composites() local
329 clk = devm_clk_regmap_register_composite(cru->dev, data->name, in rk628_clk_register_composites()
330 data->parent_names, in rk628_clk_register_composites()
331 data->num_parents, in rk628_clk_register_composites()
332 cru->regmap, in rk628_clk_register_composites()
333 data->mux_reg, in rk628_clk_register_composites()
334 data->mux_shift, in rk628_clk_register_composites()
335 data->mux_width, in rk628_clk_register_composites()
336 data->div_reg, in rk628_clk_register_composites()
337 data->div_shift, in rk628_clk_register_composites()
338 data->div_width, in rk628_clk_register_composites()
339 data->div_flags, in rk628_clk_register_composites()
340 data->gate_reg, in rk628_clk_register_composites()
341 data->gate_shift, in rk628_clk_register_composites()
342 data->flags); in rk628_clk_register_composites()
344 dev_err(cru->dev, "failed to register clock %s\n", in rk628_clk_register_composites()
345 data->name); in rk628_clk_register_composites()
349 rk628_clk_add_lookup(cru, clk, data->id); in rk628_clk_register_composites()
359 const struct clk_pll_data *data = &rk628_clk_plls[i]; in rk628_clk_register_plls() local
361 clk = devm_clk_regmap_register_pll(cru->dev, data->name, in rk628_clk_register_plls()
362 data->parent_name, in rk628_clk_register_plls()
363 cru->regmap, in rk628_clk_register_plls()
364 data->reg, in rk628_clk_register_plls()
365 data->pd_shift, in rk628_clk_register_plls()
366 data->dsmpd_shift, in rk628_clk_register_plls()
367 data->lock_shift, in rk628_clk_register_plls()
368 data->flags); in rk628_clk_register_plls()
370 dev_err(cru->dev, "failed to register clock %s\n", in rk628_clk_register_plls()
371 data->name); in rk628_clk_register_plls()
375 rk628_clk_add_lookup(cru, clk, data->id); in rk628_clk_register_plls()
381 unsigned int reg; member
388 .reg = (_reg), \
430 const struct rk628_rgu_data *data = &rk628_rgu_data[id]; in rk628_rgu_update() local
432 return regmap_write(cru->regmap, data->reg, in rk628_rgu_update()
433 BIT(data->bit + 16) | (assert << data->bit)); in rk628_rgu_update()
459 struct device *dev = cru->dev; in rk628_reset_controller_register()
461 cru->rcdev.owner = THIS_MODULE; in rk628_reset_controller_register()
462 cru->rcdev.nr_resets = ARRAY_SIZE(rk628_rgu_data); in rk628_reset_controller_register()
463 cru->rcdev.of_node = dev->of_node; in rk628_reset_controller_register()
464 cru->rcdev.ops = &rk628_rgu_ops; in rk628_reset_controller_register()
466 return devm_reset_controller_register(dev, &cru->rcdev); in rk628_reset_controller_register()
499 regmap_read(cru->parent->grf, GRF_SYSTEM_STATUS0, &val); in rk628_cru_init()
505 regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff701d); in rk628_cru_init()
508 regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0004); in rk628_cru_init()
511 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0080); in rk628_cru_init()
512 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0083); in rk628_cru_init()
514 regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff3063); in rk628_cru_init()
517 regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0005); in rk628_cru_init()
519 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0003); in rk628_cru_init()
521 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b); in rk628_cru_init()
523 regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff1028); in rk628_cru_init()
526 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff008b); in rk628_cru_init()
528 regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff1063); in rk628_cru_init()
531 regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b); in rk628_cru_init()
536 struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); in rk628_cru_probe()
537 struct device *dev = &pdev->dev; in rk628_cru_probe()
545 return -ENOMEM; in rk628_cru_probe()
547 cru->dev = dev; in rk628_cru_probe()
548 cru->parent = rk628; in rk628_cru_probe()
551 cru->regmap = devm_regmap_init_i2c(rk628->client, in rk628_cru_probe()
553 if (IS_ERR(cru->regmap)) { in rk628_cru_probe()
554 ret = PTR_ERR(cru->regmap); in rk628_cru_probe()
564 return -ENOMEM; in rk628_cru_probe()
567 clk_table[i] = ERR_PTR(-ENOENT); in rk628_cru_probe()
569 cru->clk_data.clks = clk_table; in rk628_cru_probe()
570 cru->clk_data.clk_num = CGU_NR_CLKS; in rk628_cru_probe()
580 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, in rk628_cru_probe()
581 &cru->clk_data); in rk628_cru_probe()
586 of_clk_del_provider(pdev->dev.of_node); in rk628_cru_remove()
592 { .compatible = "rockchip,rk628-cru", },
599 .name = "rk628-cru",
607 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");