15 #include "clk-regmap.h"
25 #define PLL_FBDIV(x)			HIWORD_UPDATE(x, 11, 0)
26 #define PLL_FBDIV_MASK			GENMASK(11, 0)
27 #define PLL_FBDIV_SHIFT			0
32 #define PLL_REFDIV(x)			HIWORD_UPDATE(x, 5, 0)
33 #define PLL_REFDIV_MASK			GENMASK(5, 0)
34 #define PLL_REFDIV_SHIFT		0
40 #define PLL_FRAC(x)			UPDATE(x, 23, 0)
41 #define PLL_FRAC_MASK			GENMASK(23, 0)
42 #define PLL_FRAC_SHIFT			0
68 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_recalc_rate()  local
73 	regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(0), &con0);  in clk_regmap_pll_recalc_rate()
74 	regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1);  in clk_regmap_pll_recalc_rate()
75 	regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(2), &con2);  in clk_regmap_pll_recalc_rate()
80 	dsmpd = (con1 & BIT(pll->dsmpd_shift)) >> pll->dsmpd_shift;  in clk_regmap_pll_recalc_rate()
111 	u8 _dsmpd = 1, _postdiv1 = 0, _postdiv2 = 0, _refdiv = 0;  in clk_pll_round_rate()
112 	u16 _fbdiv = 0;  in clk_pll_round_rate()
113 	u32 _frac = 0;  in clk_pll_round_rate()
123 		return -EINVAL;  in clk_pll_round_rate()
126 		return -EINVAL;  in clk_pll_round_rate()
148 			if (_postdiv1 > 0 && _postdiv1 < 8)  in clk_pll_round_rate()
153 			return -EINVAL;  in clk_pll_round_rate()
178 		frac_rate = fout - tmp;  in clk_pll_round_rate()
185 			_dsmpd = 0;  in clk_pll_round_rate()
196 	 * If DSMPD = 0 (DSM is enabled, "fractional mode")  in clk_pll_round_rate()
236 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_round_rate()  local
242 	dev_dbg(pll->dev, "%s: prate=%ld, drate=%ld, rate=%ld\n",  in clk_regmap_pll_round_rate()
252 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_set_rate()  local
260 	if (rate < 0)  in clk_regmap_pll_set_rate()
263 	dev_dbg(pll->dev, "%s: rate=%ld, bypass=%d\n",  in clk_regmap_pll_set_rate()
267 		regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(0),  in clk_regmap_pll_set_rate()
270 		regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(0),  in clk_regmap_pll_set_rate()
271 			     PLL_BYPASS(0) | PLL_POSTDIV1(postdiv1) |  in clk_regmap_pll_set_rate()
273 		regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),  in clk_regmap_pll_set_rate()
274 			     HIWORD_UPDATE(dsmpd, pll->dsmpd_shift, pll->dsmpd_shift) |  in clk_regmap_pll_set_rate()
276 		regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(2),  in clk_regmap_pll_set_rate()
279 		dev_dbg(pll->dev, "refdiv=%d, fbdiv=%d, frac=%d\n",  in clk_regmap_pll_set_rate()
281 		dev_dbg(pll->dev, "postdiv1=%d, postdiv2=%d\n",  in clk_regmap_pll_set_rate()
285 	return 0;  in clk_regmap_pll_set_rate()
290 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_prepare()  local
294 	regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),  in clk_regmap_pll_prepare()
295 		     HIWORD_UPDATE(0, pll->pd_shift, pll->pd_shift));  in clk_regmap_pll_prepare()
297 	ret = regmap_read_poll_timeout(pll->regmap,  in clk_regmap_pll_prepare()
298 				       pll->reg + PLLCON_OFFSET(1),  in clk_regmap_pll_prepare()
299 				       v, v & BIT(pll->lock_shift), 50, 50000);  in clk_regmap_pll_prepare()
301 		dev_err(pll->dev, "%s is not lock\n", clk_hw_get_name(hw));  in clk_regmap_pll_prepare()
303 	return 0;  in clk_regmap_pll_prepare()
308 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_unprepare()  local
310 	regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),  in clk_regmap_pll_unprepare()
311 		     HIWORD_UPDATE(1, pll->pd_shift, pll->pd_shift));  in clk_regmap_pll_unprepare()
316 	struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);  in clk_regmap_pll_is_prepared()  local
319 	regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1);  in clk_regmap_pll_is_prepared()
321 	return !(con1 & BIT(pll->pd_shift));  in clk_regmap_pll_is_prepared()
340 	struct clk_regmap_pll *pll;  in devm_clk_regmap_register_pll()  local
343 	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);  in devm_clk_regmap_register_pll()
344 	if (!pll)  in devm_clk_regmap_register_pll()
345 		return ERR_PTR(-ENOMEM);  in devm_clk_regmap_register_pll()
351 	init.num_parents = (parent_name ? 1 : 0);  in devm_clk_regmap_register_pll()
353 	pll->dev = dev;  in devm_clk_regmap_register_pll()
354 	pll->regmap = regmap;  in devm_clk_regmap_register_pll()
355 	pll->reg = reg;  in devm_clk_regmap_register_pll()
356 	pll->pd_shift = pd_shift;  in devm_clk_regmap_register_pll()
357 	pll->dsmpd_shift = dsmpd_shift;  in devm_clk_regmap_register_pll()
358 	pll->lock_shift = lock_shift;  in devm_clk_regmap_register_pll()
359 	pll->hw.init = &init;  in devm_clk_regmap_register_pll()
361 	return devm_clk_register(dev, &pll->hw);  in devm_clk_regmap_register_pll()