clk/rockchip/clk-rk3288.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/rk3288-cru.h>
294 	 * Clock-Architecture Diagram 1
373 	COMPOSITE(SCLK_I2S_SRC, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
424 	 * Clock-Architecture Diagram 2
427 	COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
430 	COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
444 	COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
447 	COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
451 	COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
454 	COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
458 	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
461 	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
468 	COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
472 	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
475 	COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
484 	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
490 	COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
493 	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
509 	COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
513 	COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
526 	 * Clock-Architecture Diagram 3
529 	COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
532 	COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
535 	COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
539 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
542 	COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
545 	COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
548 	COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
564 	COMPOSITE(SCLK_TSPOUT, "sclk_tspout", mux_tspout_p, 0,
567 	COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
597 	COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
600 	COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
604 	COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
642 	COMPOSITE(SCLK_MAC_PLL, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
656 	COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
681 	 * Clock-Architecture Diagram 4
862  * Some CRU registers will be reset in maskrom when the system
892 	 * Going into deep sleep (specifically setting PMU_CLR_DMA in  in rk3288_clk_suspend()
919 	for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {  in rk3288_clk_resume()
965 	clks = ctx->clk_data.clks;  in rk3288_common_init()
1005 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
1011 CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
1027 		.compatible = "rockchip,rk3288-cru",
1030 		.compatible = "rockchip,rk3288w-cru",
1039 	struct device_node *np = pdev->dev.of_node;  in clk_rk3288_probe()
1043 	match = of_match_device(clk_rk3288_match_table, &pdev->dev);  in clk_rk3288_probe()
1044 	if (!match || !match->data)  in clk_rk3288_probe()
1045 		return -EINVAL;  in clk_rk3288_probe()
1047 	init_data = match->data;  in clk_rk3288_probe()
1048 	if (init_data->inits)  in clk_rk3288_probe()
1049 		init_data->inits(np);  in clk_rk3288_probe()
1056 		.name	= "clk-rk3288",