422 			    unsigned long drate, unsigned long *prate)  in rockchip_pll_round_rate()  argument
535 						     unsigned long prate)  in rockchip_rk3036_pll_recalc_rate()  argument
539 	u64 rate64 = prate, frac_rate64 = prate;  in rockchip_rk3036_pll_recalc_rate()
628 					unsigned long prate)  in rockchip_rk3036_pll_set_rate()  argument
634 		 __func__, __clk_get_name(hw->clk), drate, prate);  in rockchip_rk3036_pll_set_rate()
788 						     unsigned long prate)  in rockchip_rk3066_pll_recalc_rate()  argument
792 	u64 rate64 = prate;  in rockchip_rk3066_pll_recalc_rate()
799 		return prate;  in rockchip_rk3066_pll_recalc_rate()
874 					unsigned long prate)  in rockchip_rk3066_pll_set_rate()  argument
878 	unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);  in rockchip_rk3066_pll_set_rate()
889 		 __func__, clk_hw_get_name(hw), old_rate, drate, prate);  in rockchip_rk3066_pll_set_rate()
1049 						     unsigned long prate)  in rockchip_rk3399_pll_recalc_rate()  argument
1053 	u64 rate64 = prate;  in rockchip_rk3399_pll_recalc_rate()
1065 		u64 frac_rate64 = prate * cur.frac;  in rockchip_rk3399_pll_recalc_rate()
1149 					unsigned long prate)  in rockchip_rk3399_pll_set_rate()  argument
1153 	unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);  in rockchip_rk3399_pll_set_rate()
1157 		 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);  in rockchip_rk3399_pll_set_rate()
1303 			    unsigned long drate, unsigned long *prate)  in rockchip_rk3588_pll_round_rate()  argument
1332 						     unsigned long prate)  in rockchip_rk3588_pll_recalc_rate()  argument
1336 	u64 rate64 = prate, postdiv;  in rockchip_rk3588_pll_recalc_rate()
1343 		return prate;  in rockchip_rk3588_pll_recalc_rate()
1350 		u64 frac_rate64 = prate * cur.k;  in rockchip_rk3588_pll_recalc_rate()
1426 					unsigned long prate)  in rockchip_rk3588_pll_set_rate()  argument
1430 	unsigned long old_rate = rockchip_rk3588_pll_recalc_rate(hw, prate);  in rockchip_rk3588_pll_set_rate()
1434 		 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);  in rockchip_rk3588_pll_set_rate()
1945 void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate)  in rockchip_boost_add_core_div()  argument
1953 	if (!pll->boost_enabled || pll->boost_backup_pll_rate == prate)  in rockchip_boost_add_core_div()
1963 	if (pll->boost_low_rate && prate > pll->boost_low_rate) {  in rockchip_boost_add_core_div()
1964 		div =  DIV_ROUND_UP(prate, pll->boost_low_rate) - 1;  in rockchip_boost_add_core_div()
1968 		pll->boost_backup_pll_rate = prate;  in rockchip_boost_add_core_div()