987 #define RK3399_PLLCON(i)			(i * 0x4)  macro
1012 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),  in rockchip_rk3399_pll_wait_lock()
1027 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_get_params()
1031 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_get_params()
1039 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_get_params()
1043 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_get_params()
1104 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
1109 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_set_params()
1117 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_set_params()
1120 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
1123 	writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
1127 		       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
1132 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
1179 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_enable()
1191 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_disable()
1197 	u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_is_enabled()
1550 		pllcon0 = RK3399_PLLCON(0);  in rockchip_pll_clk_compensation()
1551 		pllcon2 = RK3399_PLLCON(2);  in rockchip_pll_clk_compensation()