450 #define RK3036_PLLCON(i)			(i * 0x4)  macro
476 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),  in rockchip_rk3036_pll_wait_lock()
515 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_get_params()
521 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_get_params()
529 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_get_params()
594 		       pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_set_params()
602 		       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_set_params()
605 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
608 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
654 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_enable()
672 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_disable()
678 	u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_is_enabled()
1537 		pllcon0 = RK3036_PLLCON(0);  in rockchip_pll_clk_compensation()
1538 		pllcon2 = RK3036_PLLCON(2);  in rockchip_pll_clk_compensation()
1545 			       pll->reg_base + RK3036_PLLCON(1));  in rockchip_pll_clk_compensation()