77 #define MHZ			(1000UL * 1000UL)  macro
82 #define PLL_FREF_MAX		(2200 * MHZ)
84 #define PLL_FVCO_MIN		(440 * MHZ)
85 #define PLL_FVCO_MAX		(2200 * MHZ)
88 #define PLL_FOUT_MAX		(2200 * MHZ)
95 #define MIN_FOUTVCO_FREQ	(800 * MHZ)
96 #define MAX_FOUTVCO_FREQ	(2000 * MHZ)
218 	if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {  in rockchip_pll_clk_set_by_auto()
219 		fin_hz /= MHZ;  in rockchip_pll_clk_set_by_auto()
220 		foutvco /= MHZ;  in rockchip_pll_clk_set_by_auto()
234 			 fin_hz / MHZ * MHZ,  in rockchip_pll_clk_set_by_auto()
235 			 fout_hz / MHZ * MHZ);  in rockchip_pll_clk_set_by_auto()
238 		clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);  in rockchip_pll_clk_set_by_auto()
239 		rate_table->refdiv = fin_hz / MHZ / clk_gcd;  in rockchip_pll_clk_set_by_auto()
240 		rate_table->fbdiv = foutvco / MHZ / clk_gcd;  in rockchip_pll_clk_set_by_auto()
246 		f_frac = (foutvco % MHZ);  in rockchip_pll_clk_set_by_auto()
341 	u64 fvco_min = 2250 * MHZ, fvco_max = 4500 * MHZ;  in rockchip_rk3588_pll_clk_set_by_auto()
342 	u64 fout_min = 37 * MHZ, fout_max = 4500 * MHZ;  in rockchip_rk3588_pll_clk_set_by_auto()
352 	if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {  in rockchip_rk3588_pll_clk_set_by_auto()
414 		return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);  in rockchip_get_pll_settings()
416 		return rockchip_rk3588_pll_clk_set_by_auto(pll, 24 * MHZ, rate);  in rockchip_get_pll_settings()
418 		return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);  in rockchip_get_pll_settings()
1305 	if ((drate < 37 * MHZ) || (drate > 4500 * MHZ))  in rockchip_rk3588_pll_round_rate()