Lines Matching full:rate
118 int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate) in rockchip_pll_clk_rate_to_scale() argument
134 if (rate >= rate_table[i].rate) in rockchip_pll_clk_rate_to_scale()
159 return rate_table[i].rate; in rockchip_pll_clk_scale_to_rate()
396 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
402 if (rate == rate_table[i].rate) { in rockchip_get_pll_settings()
404 pll->scaling = rate; in rockchip_get_pll_settings()
414 return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
416 return rockchip_rk3588_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
418 return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
511 struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_get_params() argument
516 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
518 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
522 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
524 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
526 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) in rockchip_rk3036_pll_get_params()
530 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
564 const struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_set_params() argument
574 …pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, … in rockchip_rk3036_pll_set_params()
575 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
576 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
579 cur.rate = 0; in rockchip_rk3036_pll_set_params()
590 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
592 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
596 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
598 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
600 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
607 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
631 const struct rockchip_pll_rate_table *rate; in rockchip_rk3036_pll_set_rate() local
633 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", in rockchip_rk3036_pll_set_rate()
636 /* Get required rate settings from table */ in rockchip_rk3036_pll_set_rate()
637 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_set_rate()
638 if (!rate) { in rockchip_rk3036_pll_set_rate()
639 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3036_pll_set_rate()
644 return rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_set_rate()
686 const struct rockchip_pll_rate_table *rate; in rockchip_rk3036_pll_init() local
694 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_init()
696 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3036_pll_init()
697 if (!rate) in rockchip_rk3036_pll_init()
708 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
709 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
711 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
712 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
713 rate->dsmpd != cur.dsmpd || in rockchip_rk3036_pll_init()
714 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
723 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3036_pll_init()
725 rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_init()
768 struct rockchip_pll_rate_table *rate) in rockchip_rk3066_pll_get_params() argument
773 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) in rockchip_rk3066_pll_get_params()
775 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) in rockchip_rk3066_pll_get_params()
779 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) in rockchip_rk3066_pll_get_params()
783 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) in rockchip_rk3066_pll_get_params()
815 const struct rockchip_pll_rate_table *rate) in rockchip_rk3066_pll_set_params() argument
824 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", in rockchip_rk3066_pll_set_params()
825 __func__, rate->rate, rate->nr, rate->no, rate->nf); in rockchip_rk3066_pll_set_params()
828 cur.rate = 0; in rockchip_rk3066_pll_set_params()
841 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
843 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
847 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_params()
850 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, in rockchip_rk3066_pll_set_params()
857 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); in rockchip_rk3066_pll_set_params()
877 const struct rockchip_pll_rate_table *rate; in rockchip_rk3066_pll_set_rate() local
883 pr_debug("%s: grf regmap not available, aborting rate change\n", in rockchip_rk3066_pll_set_rate()
888 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", in rockchip_rk3066_pll_set_rate()
891 /* Get required rate settings from table */ in rockchip_rk3066_pll_set_rate()
892 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_set_rate()
893 if (!rate) { in rockchip_rk3066_pll_set_rate()
894 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3066_pll_set_rate()
899 ret = rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_set_rate()
937 const struct rockchip_pll_rate_table *rate; in rockchip_rk3066_pll_init() local
945 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_init()
947 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3066_pll_init()
948 if (!rate) in rockchip_rk3066_pll_init()
954 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
955 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); in rockchip_rk3066_pll_init()
956 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf in rockchip_rk3066_pll_init()
957 || rate->nb != cur.nb) { in rockchip_rk3066_pll_init()
958 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3066_pll_init()
960 rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_init()
1023 struct rockchip_pll_rate_table *rate) in rockchip_rk3399_pll_get_params() argument
1028 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
1032 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
1034 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
1036 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
1040 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) in rockchip_rk3399_pll_get_params()
1044 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) in rockchip_rk3399_pll_get_params()
1078 const struct rockchip_pll_rate_table *rate) in rockchip_rk3399_pll_set_params() argument
1088 …pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, … in rockchip_rk3399_pll_set_params()
1089 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
1090 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
1093 cur.rate = 0; in rockchip_rk3399_pll_set_params()
1107 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, in rockchip_rk3399_pll_set_params()
1111 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, in rockchip_rk3399_pll_set_params()
1113 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, in rockchip_rk3399_pll_set_params()
1115 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, in rockchip_rk3399_pll_set_params()
1122 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; in rockchip_rk3399_pll_set_params()
1125 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, in rockchip_rk3399_pll_set_params()
1152 const struct rockchip_pll_rate_table *rate; in rockchip_rk3399_pll_set_rate() local
1156 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", in rockchip_rk3399_pll_set_rate()
1159 /* Get required rate settings from table */ in rockchip_rk3399_pll_set_rate()
1160 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_set_rate()
1161 if (!rate) { in rockchip_rk3399_pll_set_rate()
1162 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3399_pll_set_rate()
1167 ret = rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_set_rate()
1205 const struct rockchip_pll_rate_table *rate; in rockchip_rk3399_pll_init() local
1213 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_init()
1215 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3399_pll_init()
1216 if (!rate) in rockchip_rk3399_pll_init()
1227 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3399_pll_init()
1228 rate->dsmpd, rate->frac); in rockchip_rk3399_pll_init()
1230 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3399_pll_init()
1231 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3399_pll_init()
1232 rate->dsmpd != cur.dsmpd || in rockchip_rk3399_pll_init()
1233 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3399_pll_init()
1242 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3399_pll_init()
1244 rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_init()
1312 struct rockchip_pll_rate_table *rate) in rockchip_rk3588_pll_get_params() argument
1317 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) in rockchip_rk3588_pll_get_params()
1321 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) in rockchip_rk3588_pll_get_params()
1323 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) in rockchip_rk3588_pll_get_params()
1327 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) in rockchip_rk3588_pll_get_params()
1363 const struct rockchip_pll_rate_table *rate) in rockchip_rk3588_pll_set_params() argument
1372 pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", in rockchip_rk3588_pll_set_params()
1373 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rockchip_rk3588_pll_set_params()
1376 cur.rate = 0; in rockchip_rk3588_pll_set_params()
1392 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, in rockchip_rk3588_pll_set_params()
1396 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, in rockchip_rk3588_pll_set_params()
1398 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, in rockchip_rk3588_pll_set_params()
1402 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, in rockchip_rk3588_pll_set_params()
1429 const struct rockchip_pll_rate_table *rate; in rockchip_rk3588_pll_set_rate() local
1433 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", in rockchip_rk3588_pll_set_rate()
1436 /* Get required rate settings from table */ in rockchip_rk3588_pll_set_rate()
1437 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3588_pll_set_rate()
1438 if (!rate) { in rockchip_rk3588_pll_set_rate()
1439 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3588_pll_set_rate()
1444 ret = rockchip_rk3588_pll_set_params(pll, rate); in rockchip_rk3588_pll_set_rate()
1704 for (len = 0; rate_table[len].rate != 0; ) in rockchip_clk_register_pll()
1713 "%s: could not allocate rate table for %s\n", in rockchip_clk_register_pll()
1830 pr_debug("boost-low-rate=%lu\n", pll->boost_low_rate); in rockchip_boost_init()
1841 pr_debug("boost-high-rate=%lu\n", pll->boost_high_rate); in rockchip_boost_init()
1960 * cpu clock rate should be less than or equal to in rockchip_boost_add_core_div()
1961 * low rate when change pll rate in boost module in rockchip_boost_add_core_div()