Lines Matching +full:pll +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
68 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll);
74 static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} in rockchip_boost_disable_low() argument
103 struct rockchip_clk_pll *pll; in rockchip_pll_clk_adaptive_scaling() local
106 return -EINVAL; in rockchip_pll_clk_adaptive_scaling()
108 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_adaptive_scaling()
109 if (!pll) in rockchip_pll_clk_adaptive_scaling()
110 return -EINVAL; in rockchip_pll_clk_adaptive_scaling()
112 pll->sel = sel; in rockchip_pll_clk_adaptive_scaling()
122 struct rockchip_clk_pll *pll; in rockchip_pll_clk_rate_to_scale() local
126 return -EINVAL; in rockchip_pll_clk_rate_to_scale()
128 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_rate_to_scale()
129 if (!pll) in rockchip_pll_clk_rate_to_scale()
130 return -EINVAL; in rockchip_pll_clk_rate_to_scale()
132 rate_table = pll->rate_table; in rockchip_pll_clk_rate_to_scale()
133 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_clk_rate_to_scale()
138 return -EINVAL; in rockchip_pll_clk_rate_to_scale()
146 struct rockchip_clk_pll *pll; in rockchip_pll_clk_scale_to_rate() local
150 return -EINVAL; in rockchip_pll_clk_scale_to_rate()
152 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_scale_to_rate()
153 if (!pll) in rockchip_pll_clk_scale_to_rate()
154 return -EINVAL; in rockchip_pll_clk_scale_to_rate()
156 rate_table = pll->rate_table; in rockchip_pll_clk_scale_to_rate()
157 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_clk_scale_to_rate()
162 return -EINVAL; in rockchip_pll_clk_scale_to_rate()
179 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { in rockchip_pll_clk_set_postdiv()
180 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { in rockchip_pll_clk_set_postdiv()
192 *postdiv1 = 1; in rockchip_pll_clk_set_postdiv()
193 *postdiv2 = 1; in rockchip_pll_clk_set_postdiv()
199 rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_pll_clk_set_by_auto() argument
204 /* FIXME set postdiv1/2 always 1*/ in rockchip_pll_clk_set_by_auto()
214 rate_table->postdiv1 = postdiv1; in rockchip_pll_clk_set_by_auto()
215 rate_table->postdiv2 = postdiv2; in rockchip_pll_clk_set_by_auto()
216 rate_table->dsmpd = 1; in rockchip_pll_clk_set_by_auto()
222 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
223 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
225 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
228 fin_hz, fout_hz, clk_gcd, rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
229 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
230 rate_table->postdiv2, rate_table->frac); in rockchip_pll_clk_set_by_auto()
237 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
239 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
240 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
242 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
244 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
248 do_div(fin_64, (u64)rate_table->refdiv); in rockchip_pll_clk_set_by_auto()
251 rate_table->frac = (u32)frac_64; in rockchip_pll_clk_set_by_auto()
252 if (rate_table->frac > 0) in rockchip_pll_clk_set_by_auto()
253 rate_table->dsmpd = 0; in rockchip_pll_clk_set_by_auto()
254 pr_debug("frac = %x\n", rate_table->frac); in rockchip_pll_clk_set_by_auto()
260 rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_clk_set_by_auto() argument
272 nr_out = PLL_NR_MAX + 1; in rockchip_rk3066_pll_clk_set_by_auto()
284 for (n = 1;; n++) { in rockchip_rk3066_pll_clk_set_by_auto()
290 for (no = 1; no <= PLL_NO_MAX; no++) { in rockchip_rk3066_pll_clk_set_by_auto()
291 if (!(no == 1 || !(no % 2))) in rockchip_rk3066_pll_clk_set_by_auto()
313 /* select the best from all available PLL settings */ in rockchip_rk3066_pll_clk_set_by_auto()
323 /* output the best PLL setting */ in rockchip_rk3066_pll_clk_set_by_auto()
325 rate_table->nr = nr_out; in rockchip_rk3066_pll_clk_set_by_auto()
326 rate_table->nf = nf_out; in rockchip_rk3066_pll_clk_set_by_auto()
327 rate_table->no = no_out; in rockchip_rk3066_pll_clk_set_by_auto()
336 rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_clk_set_by_auto() argument
360 rate_table->p = p; in rockchip_rk3588_pll_clk_set_by_auto()
361 rate_table->m = m; in rockchip_rk3588_pll_clk_set_by_auto()
362 rate_table->s = s; in rockchip_rk3588_pll_clk_set_by_auto()
363 rate_table->k = 0; in rockchip_rk3588_pll_clk_set_by_auto()
375 for (p = 1; p <= 4; p++) { in rockchip_rk3588_pll_clk_set_by_auto()
377 if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) { in rockchip_rk3588_pll_clk_set_by_auto()
378 rate_table->p = p; in rockchip_rk3588_pll_clk_set_by_auto()
379 rate_table->m = m; in rockchip_rk3588_pll_clk_set_by_auto()
380 rate_table->s = s; in rockchip_rk3588_pll_clk_set_by_auto()
382 ffrac = fvco - (m * fref); in rockchip_rk3588_pll_clk_set_by_auto()
384 rate_table->k = fout / fref; in rockchip_rk3588_pll_clk_set_by_auto()
396 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
398 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
401 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
403 if (i < pll->sel) { in rockchip_get_pll_settings()
404 pll->scaling = rate; in rockchip_get_pll_settings()
405 return &rate_table[pll->sel]; in rockchip_get_pll_settings()
407 pll->scaling = 0; in rockchip_get_pll_settings()
411 pll->scaling = 0; in rockchip_get_pll_settings()
413 if (pll->type == pll_rk3066) in rockchip_get_pll_settings()
414 return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
415 else if (pll->type == pll_rk3588 || pll->type == pll_rk3588_core) in rockchip_get_pll_settings()
416 return rockchip_rk3588_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
418 return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
428 * Wait for the pll to reach the locked state.
432 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
434 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
438 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
439 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
441 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_pll_wait_lock()
447 * PLL used in RK3036
467 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3036_pll_wait_lock() argument
476 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), in rockchip_rk3036_pll_wait_lock()
481 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3036_pll_wait_lock()
487 rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_con_to_rate() argument
510 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_get_params() argument
515 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
516 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
518 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
521 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
522 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
524 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
526 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) in rockchip_rk3036_pll_get_params()
529 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
530 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
537 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_recalc_rate() local
541 if (pll->sel && pll->scaling) in rockchip_rk3036_pll_recalc_rate()
542 return pll->scaling; in rockchip_rk3036_pll_recalc_rate()
544 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_recalc_rate()
563 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_set_params() argument
566 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_set_params()
567 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params()
575 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
576 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
578 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_set_params()
581 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { in rockchip_rk3036_pll_set_params()
582 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
584 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
585 rate_change_remuxed = 1; in rockchip_rk3036_pll_set_params()
589 /* update pll values */ in rockchip_rk3036_pll_set_params()
590 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
592 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
594 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
596 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
598 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
600 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
602 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
605 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
607 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
608 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
611 rockchip_boost_disable_low(pll); in rockchip_rk3036_pll_set_params()
613 /* wait for the pll to lock */ in rockchip_rk3036_pll_set_params()
614 ret = rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_set_params()
616 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3036_pll_set_params()
618 rockchip_rk3036_pll_set_params(pll, &cur); in rockchip_rk3036_pll_set_params()
622 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
630 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_set_rate() local
634 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
637 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_set_rate()
639 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3036_pll_set_rate()
640 drate, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_set_rate()
641 return -EINVAL; in rockchip_rk3036_pll_set_rate()
644 return rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_set_rate()
649 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_enable() local
650 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_enable()
651 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_enable()
654 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
655 rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_enable()
657 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_enable()
664 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_disable() local
665 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_disable()
666 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_disable()
668 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_disable()
672 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
677 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_is_enabled() local
678 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_is_enabled()
685 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_init() local
690 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3036_pll_init()
694 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_init()
700 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_init()
702 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3036_pll_init()
704 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
707 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
708 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
709 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
711 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
712 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
713 rate->dsmpd != cur.dsmpd || in rockchip_rk3036_pll_init()
714 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
715 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3036_pll_init()
719 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
723 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3036_pll_init()
724 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
725 rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_init()
749 * PLL used in RK3066, RK3188 and RK3288
752 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
763 #define RK3066_PLLCON3_RESET (1 << 5)
764 #define RK3066_PLLCON3_PWRDOWN (1 << 1)
765 #define RK3066_PLLCON3_BYPASS (1 << 0)
767 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_get_params() argument
772 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_get_params()
773 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) in rockchip_rk3066_pll_get_params()
774 & RK3066_PLLCON0_NR_MASK) + 1; in rockchip_rk3066_pll_get_params()
775 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) in rockchip_rk3066_pll_get_params()
776 & RK3066_PLLCON0_OD_MASK) + 1; in rockchip_rk3066_pll_get_params()
778 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_get_params()
779 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) in rockchip_rk3066_pll_get_params()
780 & RK3066_PLLCON1_NF_MASK) + 1; in rockchip_rk3066_pll_get_params()
782 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_get_params()
783 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) in rockchip_rk3066_pll_get_params()
784 & RK3066_PLLCON2_NB_MASK) + 1; in rockchip_rk3066_pll_get_params()
790 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_recalc_rate() local
795 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
797 pr_debug("%s: pll %s is bypassed\n", __func__, in rockchip_rk3066_pll_recalc_rate()
802 if (pll->sel && pll->scaling) in rockchip_rk3066_pll_recalc_rate()
803 return pll->scaling; in rockchip_rk3066_pll_recalc_rate()
805 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_recalc_rate()
814 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_set_params() argument
817 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3066_pll_set_params()
818 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params()
825 __func__, rate->rate, rate->nr, rate->no, rate->nf); in rockchip_rk3066_pll_set_params()
827 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_set_params()
830 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
832 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
833 rate_change_remuxed = 1; in rockchip_rk3066_pll_set_params()
838 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
840 /* update pll values */ in rockchip_rk3066_pll_set_params()
841 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
843 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
845 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params()
847 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_params()
849 pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_set_params()
850 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, in rockchip_rk3066_pll_set_params()
852 pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_set_params()
856 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
857 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); in rockchip_rk3066_pll_set_params()
859 /* wait for the pll to lock */ in rockchip_rk3066_pll_set_params()
860 ret = rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_set_params()
862 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3066_pll_set_params()
864 rockchip_rk3066_pll_set_params(pll, &cur); in rockchip_rk3066_pll_set_params()
868 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
876 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_set_rate() local
879 struct regmap *grf = pll->ctx->grf; in rockchip_rk3066_pll_set_rate()
892 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_set_rate()
894 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3066_pll_set_rate()
896 return -EINVAL; in rockchip_rk3066_pll_set_rate()
899 ret = rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_set_rate()
901 pll->scaling = 0; in rockchip_rk3066_pll_set_rate()
908 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_enable() local
911 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
912 rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_enable()
919 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_disable() local
923 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable()
928 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_is_enabled() local
929 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_is_enabled()
936 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_init() local
941 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3066_pll_init()
945 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_init()
951 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_init()
953 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", in rockchip_rk3066_pll_init()
954 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
955 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); in rockchip_rk3066_pll_init()
956 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf in rockchip_rk3066_pll_init()
957 || rate->nb != cur.nb) { in rockchip_rk3066_pll_init()
958 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3066_pll_init()
960 rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_init()
984 * PLL used in RK3399
1003 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3399_pll_wait_lock() argument
1012 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), in rockchip_rk3399_pll_wait_lock()
1017 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3399_pll_wait_lock()
1022 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_get_params() argument
1027 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_get_params()
1028 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
1031 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_get_params()
1032 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
1034 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
1036 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
1039 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_get_params()
1040 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) in rockchip_rk3399_pll_get_params()
1043 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_get_params()
1044 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) in rockchip_rk3399_pll_get_params()
1051 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_recalc_rate() local
1055 if (pll->sel && pll->scaling) in rockchip_rk3399_pll_recalc_rate()
1056 return pll->scaling; in rockchip_rk3399_pll_recalc_rate()
1058 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_recalc_rate()
1077 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_set_params() argument
1080 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3399_pll_set_params()
1081 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params()
1089 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
1090 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
1092 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_set_params()
1095 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3399_pll_set_params()
1097 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
1098 rate_change_remuxed = 1; in rockchip_rk3399_pll_set_params()
1101 /* set pll power down */ in rockchip_rk3399_pll_set_params()
1104 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1106 /* update pll values */ in rockchip_rk3399_pll_set_params()
1107 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, in rockchip_rk3399_pll_set_params()
1109 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_set_params()
1111 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, in rockchip_rk3399_pll_set_params()
1113 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, in rockchip_rk3399_pll_set_params()
1115 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, in rockchip_rk3399_pll_set_params()
1117 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_set_params()
1120 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
1122 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; in rockchip_rk3399_pll_set_params()
1123 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
1125 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, in rockchip_rk3399_pll_set_params()
1127 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1129 /* set pll power up */ in rockchip_rk3399_pll_set_params()
1132 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1134 /* wait for the pll to lock */ in rockchip_rk3399_pll_set_params()
1135 ret = rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_set_params()
1137 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3399_pll_set_params()
1139 rockchip_rk3399_pll_set_params(pll, &cur); in rockchip_rk3399_pll_set_params()
1143 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
1151 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_set_rate() local
1157 __func__, __clk_get_name(hw->clk), old_rate, drate, prate); in rockchip_rk3399_pll_set_rate()
1160 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_set_rate()
1162 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3399_pll_set_rate()
1163 drate, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_set_rate()
1164 return -EINVAL; in rockchip_rk3399_pll_set_rate()
1167 ret = rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_set_rate()
1169 pll->scaling = 0; in rockchip_rk3399_pll_set_rate()
1176 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_enable() local
1179 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_enable()
1180 rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_enable()
1187 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_disable() local
1191 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_disable()
1196 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_is_enabled() local
1197 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_is_enabled()
1204 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_init() local
1209 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3399_pll_init()
1213 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_init()
1219 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_init()
1221 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3399_pll_init()
1223 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
1226 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
1227 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3399_pll_init()
1228 rate->dsmpd, rate->frac); in rockchip_rk3399_pll_init()
1230 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3399_pll_init()
1231 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3399_pll_init()
1232 rate->dsmpd != cur.dsmpd || in rockchip_rk3399_pll_init()
1233 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3399_pll_init()
1234 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3399_pll_init()
1238 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
1242 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3399_pll_init()
1243 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
1244 rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_init()
1268 * PLL used in RK3588
1283 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3588_pll_wait_lock() argument
1292 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), in rockchip_rk3588_pll_wait_lock()
1297 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3588_pll_wait_lock()
1306 return -EINVAL; in rockchip_rk3588_pll_round_rate()
1311 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_get_params() argument
1316 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_get_params()
1317 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) in rockchip_rk3588_pll_get_params()
1320 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_get_params()
1321 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) in rockchip_rk3588_pll_get_params()
1323 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) in rockchip_rk3588_pll_get_params()
1326 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_get_params()
1327 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) in rockchip_rk3588_pll_get_params()
1334 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_recalc_rate() local
1338 if (pll->sel && pll->scaling) in rockchip_rk3588_pll_recalc_rate()
1339 return pll->scaling; in rockchip_rk3588_pll_recalc_rate()
1341 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_recalc_rate()
1362 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_set_params() argument
1365 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_set_params()
1366 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_set_params()
1373 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rockchip_rk3588_pll_set_params()
1375 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_set_params()
1378 if (pll->type == pll_rk3588) { in rockchip_rk3588_pll_set_params()
1379 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3588_pll_set_params()
1381 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
1382 rate_change_remuxed = 1; in rockchip_rk3588_pll_set_params()
1386 /* set pll power down */ in rockchip_rk3588_pll_set_params()
1389 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1391 /* update pll values */ in rockchip_rk3588_pll_set_params()
1392 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, in rockchip_rk3588_pll_set_params()
1394 pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_set_params()
1396 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, in rockchip_rk3588_pll_set_params()
1398 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, in rockchip_rk3588_pll_set_params()
1400 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1402 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, in rockchip_rk3588_pll_set_params()
1404 pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_set_params()
1406 /* set pll power up */ in rockchip_rk3588_pll_set_params()
1409 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1411 /* wait for the pll to lock */ in rockchip_rk3588_pll_set_params()
1412 ret = rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_set_params()
1414 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3588_pll_set_params()
1416 rockchip_rk3588_pll_set_params(pll, &cur); in rockchip_rk3588_pll_set_params()
1419 if ((pll->type == pll_rk3588) && rate_change_remuxed) in rockchip_rk3588_pll_set_params()
1420 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
1428 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_set_rate() local
1434 __func__, __clk_get_name(hw->clk), old_rate, drate, prate); in rockchip_rk3588_pll_set_rate()
1437 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3588_pll_set_rate()
1439 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3588_pll_set_rate()
1440 drate, __clk_get_name(hw->clk)); in rockchip_rk3588_pll_set_rate()
1441 return -EINVAL; in rockchip_rk3588_pll_set_rate()
1444 ret = rockchip_rk3588_pll_set_params(pll, rate); in rockchip_rk3588_pll_set_rate()
1446 pll->scaling = 0; in rockchip_rk3588_pll_set_rate()
1453 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_enable() local
1454 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_enable()
1455 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_enable()
1458 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_enable()
1459 rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_enable()
1461 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_enable()
1468 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_disable() local
1469 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_disable()
1470 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_disable()
1472 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_disable()
1476 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_disable()
1481 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_is_enabled() local
1482 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_is_enabled()
1489 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_init() local
1491 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3588_pll_init()
1518 struct rockchip_clk_pll *pll; in rockchip_pll_clk_compensation() local
1524 if ((ppm > 1000) || (ppm < -1000)) in rockchip_pll_clk_compensation()
1525 return -EINVAL; in rockchip_pll_clk_compensation()
1528 return -EINVAL; in rockchip_pll_clk_compensation()
1530 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_compensation()
1531 if (!pll) in rockchip_pll_clk_compensation()
1532 return -EINVAL; in rockchip_pll_clk_compensation()
1534 switch (pll->type) { in rockchip_pll_clk_compensation()
1545 pll->reg_base + RK3036_PLLCON(1)); in rockchip_pll_clk_compensation()
1548 return -EINVAL; in rockchip_pll_clk_compensation()
1564 return -EINVAL; in rockchip_pll_clk_compensation()
1568 ppm = negative ? ~ppm + 1 : ppm; in rockchip_pll_clk_compensation()
1571 frac = readl_relaxed(pll->reg_base + pllcon2) & frac_mask; in rockchip_pll_clk_compensation()
1572 fbdiv = readl_relaxed(pll->reg_base + pllcon0) & fbdiv_mask; in rockchip_pll_clk_compensation()
1575 switch (pll->type) { in rockchip_pll_clk_compensation()
1582 * -------------- = (fbdiv + ----------) * --------- in rockchip_pll_clk_compensation()
1583 * 1 << 24 1 << 24 1000000 in rockchip_pll_clk_compensation()
1589 fracdiv = negative ? frac - (m + n) : frac + (m + n); in rockchip_pll_clk_compensation()
1592 return -EINVAL; in rockchip_pll_clk_compensation()
1594 pllcon = readl_relaxed(pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1597 writel_relaxed(pllcon, pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1603 fracdiv = negative ? frac - (div64_u64(m + n, 10)) : frac + (div64_u64(m + n, 10)); in rockchip_pll_clk_compensation()
1606 return -EINVAL; in rockchip_pll_clk_compensation()
1609 pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1612 return -EINVAL; in rockchip_pll_clk_compensation()
1621 * Common registering of pll clocks
1634 struct rockchip_clk_pll *pll; in rockchip_clk_register_pll() local
1640 (pll_type == pll_rk3328 && num_parents != 1)) { in rockchip_clk_register_pll()
1642 return ERR_PTR(-EINVAL); in rockchip_clk_register_pll()
1645 /* name the actual pll */ in rockchip_clk_register_pll()
1648 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in rockchip_clk_register_pll()
1649 if (!pll) in rockchip_clk_register_pll()
1650 return ERR_PTR(-ENOMEM); in rockchip_clk_register_pll()
1652 /* create the mux on top of the real pll */ in rockchip_clk_register_pll()
1653 pll->pll_mux_ops = &clk_mux_ops; in rockchip_clk_register_pll()
1654 pll_mux = &pll->pll_mux; in rockchip_clk_register_pll()
1655 pll_mux->reg = ctx->reg_base + mode_offset; in rockchip_clk_register_pll()
1656 pll_mux->shift = mode_shift; in rockchip_clk_register_pll()
1658 pll_mux->mask = PLL_RK3328_MODE_MASK; in rockchip_clk_register_pll()
1660 pll_mux->mask = PLL_MODE_MASK; in rockchip_clk_register_pll()
1661 pll_mux->flags = 0; in rockchip_clk_register_pll()
1662 pll_mux->lock = &ctx->lock; in rockchip_clk_register_pll()
1663 pll_mux->hw.init = &init; in rockchip_clk_register_pll()
1664 pll_mux->flags |= CLK_MUX_HIWORD_MASK; in rockchip_clk_register_pll()
1666 /* the actual muxing is xin24m, pll-output, xin32k */ in rockchip_clk_register_pll()
1668 pll_parents[1] = pll_name; in rockchip_clk_register_pll()
1669 pll_parents[2] = parent_names[1]; in rockchip_clk_register_pll()
1673 init.ops = pll->pll_mux_ops; in rockchip_clk_register_pll()
1680 mux_clk = clk_register(NULL, &pll_mux->hw); in rockchip_clk_register_pll()
1684 /* now create the actual pll */ in rockchip_clk_register_pll()
1698 init.num_parents = 1; in rockchip_clk_register_pll()
1707 pll->rate_count = len; in rockchip_clk_register_pll()
1708 pll->rate_table = kmemdup(rate_table, in rockchip_clk_register_pll()
1709 pll->rate_count * in rockchip_clk_register_pll()
1712 WARN(!pll->rate_table, in rockchip_clk_register_pll()
1720 if (!pll->rate_table) in rockchip_clk_register_pll()
1727 if (!pll->rate_table || IS_ERR(ctx->grf)) in rockchip_clk_register_pll()
1735 if (!pll->rate_table) in rockchip_clk_register_pll()
1744 if (!pll->rate_table) in rockchip_clk_register_pll()
1752 pr_warn("%s: Unknown pll type for pll clk %s\n", in rockchip_clk_register_pll()
1756 pll->hw.init = &init; in rockchip_clk_register_pll()
1757 pll->type = pll_type; in rockchip_clk_register_pll()
1758 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
1759 pll->lock_offset = grf_lock_offset; in rockchip_clk_register_pll()
1760 pll->lock_shift = lock_shift; in rockchip_clk_register_pll()
1761 pll->flags = clk_pll_flags; in rockchip_clk_register_pll()
1762 pll->lock = &ctx->lock; in rockchip_clk_register_pll()
1763 pll->ctx = ctx; in rockchip_clk_register_pll()
1765 pll_clk = clk_register(NULL, &pll->hw); in rockchip_clk_register_pll()
1767 pr_err("%s: failed to register pll clock %s : %ld\n", in rockchip_clk_register_pll()
1778 kfree(pll); in rockchip_clk_register_pll()
1783 static unsigned long rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, in rockchip_pll_con_to_rate() argument
1786 switch (pll->type) { in rockchip_pll_con_to_rate()
1789 return rockchip_rk3036_pll_con_to_rate(pll, con0, con1); in rockchip_pll_con_to_rate()
1795 pr_warn("%s: Unknown pll type\n", __func__); in rockchip_pll_con_to_rate()
1803 struct rockchip_clk_pll *pll; in rockchip_boost_init() local
1809 pll = to_rockchip_clk_pll(hw); in rockchip_boost_init()
1810 np = of_parse_phandle(pll->ctx->cru_node, "rockchip,boost", 0); in rockchip_boost_init()
1815 pll->boost = syscon_node_to_regmap(np); in rockchip_boost_init()
1816 if (IS_ERR(pll->boost)) { in rockchip_boost_init()
1821 if (!of_property_read_u32(np, "rockchip,boost-low-con0", &con0) && in rockchip_boost_init()
1822 !of_property_read_u32(np, "rockchip,boost-low-con1", &con1)) { in rockchip_boost_init()
1823 pr_debug("boost-low-con=0x%x 0x%x\n", con0, con1); in rockchip_boost_init()
1824 regmap_write(pll->boost, BOOST_PLL_L_CON(0), in rockchip_boost_init()
1826 regmap_write(pll->boost, BOOST_PLL_L_CON(1), in rockchip_boost_init()
1828 pll->boost_low_rate = rockchip_pll_con_to_rate(pll, con0, in rockchip_boost_init()
1830 pr_debug("boost-low-rate=%lu\n", pll->boost_low_rate); in rockchip_boost_init()
1832 if (!of_property_read_u32(np, "rockchip,boost-high-con0", &con0) && in rockchip_boost_init()
1833 !of_property_read_u32(np, "rockchip,boost-high-con1", &con1)) { in rockchip_boost_init()
1834 pr_debug("boost-high-con=0x%x 0x%x\n", con0, con1); in rockchip_boost_init()
1835 regmap_write(pll->boost, BOOST_PLL_H_CON(0), in rockchip_boost_init()
1837 regmap_write(pll->boost, BOOST_PLL_H_CON(1), in rockchip_boost_init()
1839 pll->boost_high_rate = rockchip_pll_con_to_rate(pll, con0, in rockchip_boost_init()
1841 pr_debug("boost-high-rate=%lu\n", pll->boost_high_rate); in rockchip_boost_init()
1843 if (!of_property_read_u32(np, "rockchip,boost-backup-pll", &value)) { in rockchip_boost_init()
1844 pr_debug("boost-backup-pll=0x%x\n", value); in rockchip_boost_init()
1845 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_init()
1849 if (!of_property_read_u32(np, "rockchip,boost-backup-pll-usage", in rockchip_boost_init()
1850 &pll->boost_backup_pll_usage)) { in rockchip_boost_init()
1851 pr_debug("boost-backup-pll-usage=0x%x\n", in rockchip_boost_init()
1852 pll->boost_backup_pll_usage); in rockchip_boost_init()
1853 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_init()
1854 HIWORD_UPDATE(pll->boost_backup_pll_usage, in rockchip_boost_init()
1858 if (!of_property_read_u32(np, "rockchip,boost-switch-threshold", in rockchip_boost_init()
1860 pr_debug("boost-switch-threshold=0x%x\n", value); in rockchip_boost_init()
1861 regmap_write(pll->boost, BOOST_SWITCH_THRESHOLD, value); in rockchip_boost_init()
1863 if (!of_property_read_u32(np, "rockchip,boost-statis-threshold", in rockchip_boost_init()
1865 pr_debug("boost-statis-threshold=0x%x\n", value); in rockchip_boost_init()
1866 regmap_write(pll->boost, BOOST_STATIS_THRESHOLD, value); in rockchip_boost_init()
1868 if (!of_property_read_u32(np, "rockchip,boost-statis-enable", in rockchip_boost_init()
1870 pr_debug("boost-statis-enable=0x%x\n", value); in rockchip_boost_init()
1871 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_init()
1875 if (!of_property_read_u32(np, "rockchip,boost-enable", &value)) { in rockchip_boost_init()
1876 pr_debug("boost-enable=0x%x\n", value); in rockchip_boost_init()
1877 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_init()
1881 pll->boost_enabled = true; in rockchip_boost_init()
1884 if (pll->boost_enabled) { in rockchip_boost_init()
1886 hlist_add_head(&pll->debug_node, &clk_boost_list); in rockchip_boost_init()
1894 struct rockchip_clk_pll *pll; in rockchip_boost_enable_recovery_sw_low() local
1899 pll = to_rockchip_clk_pll(hw); in rockchip_boost_enable_recovery_sw_low()
1900 if (!pll->boost_enabled) in rockchip_boost_enable_recovery_sw_low()
1903 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_enable_recovery_sw_low()
1904 HIWORD_UPDATE(1, BOOST_RECOVERY_MASK, in rockchip_boost_enable_recovery_sw_low()
1907 regmap_read(pll->boost, BOOST_FSM_STATUS, &val); in rockchip_boost_enable_recovery_sw_low()
1910 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_enable_recovery_sw_low()
1911 HIWORD_UPDATE(1, BOOST_SW_CTRL_MASK, in rockchip_boost_enable_recovery_sw_low()
1913 HIWORD_UPDATE(1, BOOST_LOW_FREQ_EN_MASK, in rockchip_boost_enable_recovery_sw_low()
1917 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) in rockchip_boost_disable_low() argument
1919 if (!pll->boost_enabled) in rockchip_boost_disable_low()
1922 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_low()
1929 struct rockchip_clk_pll *pll; in rockchip_boost_disable_recovery_sw() local
1933 pll = to_rockchip_clk_pll(hw); in rockchip_boost_disable_recovery_sw()
1934 if (!pll->boost_enabled) in rockchip_boost_disable_recovery_sw()
1937 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_recovery_sw()
1940 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_recovery_sw()
1947 struct rockchip_clk_pll *pll; in rockchip_boost_add_core_div() local
1952 pll = to_rockchip_clk_pll(hw); in rockchip_boost_add_core_div()
1953 if (!pll->boost_enabled || pll->boost_backup_pll_rate == prate) in rockchip_boost_add_core_div()
1957 if (pll->boost_backup_pll_usage == BOOST_BACKUP_PLL_USAGE_TARGET) in rockchip_boost_add_core_div()
1961 * low rate when change pll rate in boost module in rockchip_boost_add_core_div()
1963 if (pll->boost_low_rate && prate > pll->boost_low_rate) { in rockchip_boost_add_core_div()
1964 div = DIV_ROUND_UP(prate, pll->boost_low_rate) - 1; in rockchip_boost_add_core_div()
1965 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_add_core_div()
1968 pll->boost_backup_pll_rate = prate; in rockchip_boost_add_core_div()
1978 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; in boost_summary_show() local
1986 …seq_puts(s, "-------------------------------------------------------------------------------------… in boost_summary_show()
1987 seq_printf(s, " %s\n", clk_hw_get_name(&pll->hw)); in boost_summary_show()
1989 regmap_read(pll->boost, BOOST_SWITCH_CNT, &boost_count); in boost_summary_show()
1991 regmap_read(pll->boost, BOOST_HIGH_PERF_CNT0, &freq_cnt0); in boost_summary_show()
1992 regmap_read(pll->boost, BOOST_HIGH_PERF_CNT1, &freq_cnt1); in boost_summary_show()
1997 regmap_read(pll->boost, BOOST_SHORT_SWITCH_CNT, &short_count); in boost_summary_show()
1998 regmap_read(pll->boost, BOOST_STATIS_THRESHOLD, &short_threshold); in boost_summary_show()
1999 regmap_read(pll->boost, BOOST_SWITCH_THRESHOLD, &interval_time); in boost_summary_show()
2010 return single_open(file, boost_summary_show, inode->i_private); in boost_summary_open()
2022 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; in boost_config_show() local
2024 seq_printf(s, "boost_enabled: %d\n", pll->boost_enabled); in boost_config_show()
2025 seq_printf(s, "boost_low_rate: %lu\n", pll->boost_low_rate); in boost_config_show()
2026 seq_printf(s, "boost_high_rate: %lu\n", pll->boost_high_rate); in boost_config_show()
2033 return single_open(file, boost_config_show, inode->i_private); in boost_config_open()
2043 static int boost_debug_create_one(struct rockchip_clk_pll *pll, in boost_debug_create_one() argument
2048 pdentry = debugfs_lookup(clk_hw_get_name(&pll->hw), rootdir); in boost_debug_create_one()
2051 clk_hw_get_name(&pll->hw)); in boost_debug_create_one()
2052 return -ENOMEM; in boost_debug_create_one()
2056 pll, &boost_summary_fops); in boost_debug_create_one()
2059 return -ENOMEM; in boost_debug_create_one()
2063 pll, &boost_config_fops); in boost_debug_create_one()
2066 return -ENOMEM; in boost_debug_create_one()
2074 struct rockchip_clk_pll *pll; in boost_debug_init() local
2080 return -ENOMEM; in boost_debug_init()
2085 hlist_for_each_entry(pll, &clk_boost_list, debug_node) in boost_debug_init()
2086 boost_debug_create_one(pll, rootdir); in boost_debug_init()