Lines Matching full:pll
68 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll);
74 static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} in rockchip_boost_disable_low() argument
103 struct rockchip_clk_pll *pll; in rockchip_pll_clk_adaptive_scaling() local
108 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_adaptive_scaling()
109 if (!pll) in rockchip_pll_clk_adaptive_scaling()
112 pll->sel = sel; in rockchip_pll_clk_adaptive_scaling()
122 struct rockchip_clk_pll *pll; in rockchip_pll_clk_rate_to_scale() local
128 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_rate_to_scale()
129 if (!pll) in rockchip_pll_clk_rate_to_scale()
132 rate_table = pll->rate_table; in rockchip_pll_clk_rate_to_scale()
133 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_clk_rate_to_scale()
146 struct rockchip_clk_pll *pll; in rockchip_pll_clk_scale_to_rate() local
152 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_scale_to_rate()
153 if (!pll) in rockchip_pll_clk_scale_to_rate()
156 rate_table = pll->rate_table; in rockchip_pll_clk_scale_to_rate()
157 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_clk_scale_to_rate()
199 rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_pll_clk_set_by_auto() argument
260 rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_clk_set_by_auto() argument
313 /* select the best from all available PLL settings */ in rockchip_rk3066_pll_clk_set_by_auto()
323 /* output the best PLL setting */ in rockchip_rk3066_pll_clk_set_by_auto()
336 rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_clk_set_by_auto() argument
396 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
398 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
401 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
403 if (i < pll->sel) { in rockchip_get_pll_settings()
404 pll->scaling = rate; in rockchip_get_pll_settings()
405 return &rate_table[pll->sel]; in rockchip_get_pll_settings()
407 pll->scaling = 0; in rockchip_get_pll_settings()
411 pll->scaling = 0; in rockchip_get_pll_settings()
413 if (pll->type == pll_rk3066) in rockchip_get_pll_settings()
414 return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
415 else if (pll->type == pll_rk3588 || pll->type == pll_rk3588_core) in rockchip_get_pll_settings()
416 return rockchip_rk3588_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
418 return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate); in rockchip_get_pll_settings()
428 * Wait for the pll to reach the locked state.
432 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
434 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
438 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
439 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
441 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_pll_wait_lock()
447 * PLL used in RK3036
467 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3036_pll_wait_lock() argument
476 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), in rockchip_rk3036_pll_wait_lock()
481 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3036_pll_wait_lock()
487 rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_con_to_rate() argument
510 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_get_params() argument
515 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
521 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
529 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
537 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_recalc_rate() local
541 if (pll->sel && pll->scaling) in rockchip_rk3036_pll_recalc_rate()
542 return pll->scaling; in rockchip_rk3036_pll_recalc_rate()
544 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_recalc_rate()
563 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_set_params() argument
566 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_set_params()
567 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params()
578 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_set_params()
581 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { in rockchip_rk3036_pll_set_params()
589 /* update pll values */ in rockchip_rk3036_pll_set_params()
594 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
602 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
605 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
608 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
611 rockchip_boost_disable_low(pll); in rockchip_rk3036_pll_set_params()
613 /* wait for the pll to lock */ in rockchip_rk3036_pll_set_params()
614 ret = rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_set_params()
616 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3036_pll_set_params()
618 rockchip_rk3036_pll_set_params(pll, &cur); in rockchip_rk3036_pll_set_params()
630 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_set_rate() local
637 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_set_rate()
639 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3036_pll_set_rate()
644 return rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_set_rate()
649 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_enable() local
650 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_enable()
651 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_enable()
654 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
655 rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_enable()
664 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_disable() local
665 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_disable()
666 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_disable()
672 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
677 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_is_enabled() local
678 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_is_enabled()
685 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_init() local
690 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3036_pll_init()
694 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_init()
700 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_init()
702 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3036_pll_init()
723 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3036_pll_init()
725 rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_init()
749 * PLL used in RK3066, RK3188 and RK3288
767 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_get_params() argument
772 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_get_params()
778 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_get_params()
782 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_get_params()
790 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_recalc_rate() local
795 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
797 pr_debug("%s: pll %s is bypassed\n", __func__, in rockchip_rk3066_pll_recalc_rate()
802 if (pll->sel && pll->scaling) in rockchip_rk3066_pll_recalc_rate()
803 return pll->scaling; in rockchip_rk3066_pll_recalc_rate()
805 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_recalc_rate()
814 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_set_params() argument
817 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3066_pll_set_params()
818 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params()
827 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_set_params()
838 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
840 /* update pll values */ in rockchip_rk3066_pll_set_params()
845 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params()
849 pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_set_params()
852 pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_set_params()
856 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
859 /* wait for the pll to lock */ in rockchip_rk3066_pll_set_params()
860 ret = rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_set_params()
862 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3066_pll_set_params()
864 rockchip_rk3066_pll_set_params(pll, &cur); in rockchip_rk3066_pll_set_params()
876 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_set_rate() local
879 struct regmap *grf = pll->ctx->grf; in rockchip_rk3066_pll_set_rate()
892 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_set_rate()
894 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3066_pll_set_rate()
899 ret = rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_set_rate()
901 pll->scaling = 0; in rockchip_rk3066_pll_set_rate()
908 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_enable() local
911 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
912 rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_enable()
919 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_disable() local
923 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable()
928 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_is_enabled() local
929 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_is_enabled()
936 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_init() local
941 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3066_pll_init()
945 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_init()
951 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_init()
953 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", in rockchip_rk3066_pll_init()
958 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3066_pll_init()
960 rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_init()
984 * PLL used in RK3399
1003 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3399_pll_wait_lock() argument
1012 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), in rockchip_rk3399_pll_wait_lock()
1017 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3399_pll_wait_lock()
1022 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_get_params() argument
1027 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_get_params()
1031 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_get_params()
1039 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_get_params()
1043 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_get_params()
1051 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_recalc_rate() local
1055 if (pll->sel && pll->scaling) in rockchip_rk3399_pll_recalc_rate()
1056 return pll->scaling; in rockchip_rk3399_pll_recalc_rate()
1058 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_recalc_rate()
1077 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_set_params() argument
1080 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3399_pll_set_params()
1081 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params()
1092 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_set_params()
1101 /* set pll power down */ in rockchip_rk3399_pll_set_params()
1104 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1106 /* update pll values */ in rockchip_rk3399_pll_set_params()
1109 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_set_params()
1117 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_set_params()
1120 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
1123 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
1127 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1129 /* set pll power up */ in rockchip_rk3399_pll_set_params()
1132 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
1134 /* wait for the pll to lock */ in rockchip_rk3399_pll_set_params()
1135 ret = rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_set_params()
1137 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3399_pll_set_params()
1139 rockchip_rk3399_pll_set_params(pll, &cur); in rockchip_rk3399_pll_set_params()
1151 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_set_rate() local
1160 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_set_rate()
1162 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3399_pll_set_rate()
1167 ret = rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_set_rate()
1169 pll->scaling = 0; in rockchip_rk3399_pll_set_rate()
1176 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_enable() local
1179 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_enable()
1180 rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_enable()
1187 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_disable() local
1191 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_disable()
1196 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_is_enabled() local
1197 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_is_enabled()
1204 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_init() local
1209 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3399_pll_init()
1213 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_init()
1219 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_init()
1221 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3399_pll_init()
1242 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3399_pll_init()
1244 rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_init()
1268 * PLL used in RK3588
1283 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3588_pll_wait_lock() argument
1292 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), in rockchip_rk3588_pll_wait_lock()
1297 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3588_pll_wait_lock()
1311 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_get_params() argument
1316 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_get_params()
1320 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_get_params()
1326 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_get_params()
1334 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_recalc_rate() local
1338 if (pll->sel && pll->scaling) in rockchip_rk3588_pll_recalc_rate()
1339 return pll->scaling; in rockchip_rk3588_pll_recalc_rate()
1341 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_recalc_rate()
1362 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_set_params() argument
1365 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_set_params()
1366 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_set_params()
1375 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_set_params()
1378 if (pll->type == pll_rk3588) { in rockchip_rk3588_pll_set_params()
1386 /* set pll power down */ in rockchip_rk3588_pll_set_params()
1389 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1391 /* update pll values */ in rockchip_rk3588_pll_set_params()
1394 pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_set_params()
1400 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1404 pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_set_params()
1406 /* set pll power up */ in rockchip_rk3588_pll_set_params()
1409 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
1411 /* wait for the pll to lock */ in rockchip_rk3588_pll_set_params()
1412 ret = rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_set_params()
1414 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3588_pll_set_params()
1416 rockchip_rk3588_pll_set_params(pll, &cur); in rockchip_rk3588_pll_set_params()
1419 if ((pll->type == pll_rk3588) && rate_change_remuxed) in rockchip_rk3588_pll_set_params()
1428 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_set_rate() local
1437 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3588_pll_set_rate()
1439 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3588_pll_set_rate()
1444 ret = rockchip_rk3588_pll_set_params(pll, rate); in rockchip_rk3588_pll_set_rate()
1446 pll->scaling = 0; in rockchip_rk3588_pll_set_rate()
1453 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_enable() local
1454 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_enable()
1455 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_enable()
1458 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_enable()
1459 rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_enable()
1468 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_disable() local
1469 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_disable()
1470 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_disable()
1476 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_disable()
1481 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_is_enabled() local
1482 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_is_enabled()
1489 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_init() local
1491 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3588_pll_init()
1518 struct rockchip_clk_pll *pll; in rockchip_pll_clk_compensation() local
1530 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_compensation()
1531 if (!pll) in rockchip_pll_clk_compensation()
1534 switch (pll->type) { in rockchip_pll_clk_compensation()
1545 pll->reg_base + RK3036_PLLCON(1)); in rockchip_pll_clk_compensation()
1571 frac = readl_relaxed(pll->reg_base + pllcon2) & frac_mask; in rockchip_pll_clk_compensation()
1572 fbdiv = readl_relaxed(pll->reg_base + pllcon0) & fbdiv_mask; in rockchip_pll_clk_compensation()
1575 switch (pll->type) { in rockchip_pll_clk_compensation()
1594 pllcon = readl_relaxed(pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1597 writel_relaxed(pllcon, pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1609 pll->reg_base + pllcon2); in rockchip_pll_clk_compensation()
1621 * Common registering of pll clocks
1634 struct rockchip_clk_pll *pll; in rockchip_clk_register_pll() local
1645 /* name the actual pll */ in rockchip_clk_register_pll()
1648 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in rockchip_clk_register_pll()
1649 if (!pll) in rockchip_clk_register_pll()
1652 /* create the mux on top of the real pll */ in rockchip_clk_register_pll()
1653 pll->pll_mux_ops = &clk_mux_ops; in rockchip_clk_register_pll()
1654 pll_mux = &pll->pll_mux; in rockchip_clk_register_pll()
1666 /* the actual muxing is xin24m, pll-output, xin32k */ in rockchip_clk_register_pll()
1673 init.ops = pll->pll_mux_ops; in rockchip_clk_register_pll()
1684 /* now create the actual pll */ in rockchip_clk_register_pll()
1707 pll->rate_count = len; in rockchip_clk_register_pll()
1708 pll->rate_table = kmemdup(rate_table, in rockchip_clk_register_pll()
1709 pll->rate_count * in rockchip_clk_register_pll()
1712 WARN(!pll->rate_table, in rockchip_clk_register_pll()
1720 if (!pll->rate_table) in rockchip_clk_register_pll()
1727 if (!pll->rate_table || IS_ERR(ctx->grf)) in rockchip_clk_register_pll()
1735 if (!pll->rate_table) in rockchip_clk_register_pll()
1744 if (!pll->rate_table) in rockchip_clk_register_pll()
1752 pr_warn("%s: Unknown pll type for pll clk %s\n", in rockchip_clk_register_pll()
1756 pll->hw.init = &init; in rockchip_clk_register_pll()
1757 pll->type = pll_type; in rockchip_clk_register_pll()
1758 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
1759 pll->lock_offset = grf_lock_offset; in rockchip_clk_register_pll()
1760 pll->lock_shift = lock_shift; in rockchip_clk_register_pll()
1761 pll->flags = clk_pll_flags; in rockchip_clk_register_pll()
1762 pll->lock = &ctx->lock; in rockchip_clk_register_pll()
1763 pll->ctx = ctx; in rockchip_clk_register_pll()
1765 pll_clk = clk_register(NULL, &pll->hw); in rockchip_clk_register_pll()
1767 pr_err("%s: failed to register pll clock %s : %ld\n", in rockchip_clk_register_pll()
1778 kfree(pll); in rockchip_clk_register_pll()
1783 static unsigned long rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, in rockchip_pll_con_to_rate() argument
1786 switch (pll->type) { in rockchip_pll_con_to_rate()
1789 return rockchip_rk3036_pll_con_to_rate(pll, con0, con1); in rockchip_pll_con_to_rate()
1795 pr_warn("%s: Unknown pll type\n", __func__); in rockchip_pll_con_to_rate()
1803 struct rockchip_clk_pll *pll; in rockchip_boost_init() local
1809 pll = to_rockchip_clk_pll(hw); in rockchip_boost_init()
1810 np = of_parse_phandle(pll->ctx->cru_node, "rockchip,boost", 0); in rockchip_boost_init()
1815 pll->boost = syscon_node_to_regmap(np); in rockchip_boost_init()
1816 if (IS_ERR(pll->boost)) { in rockchip_boost_init()
1824 regmap_write(pll->boost, BOOST_PLL_L_CON(0), in rockchip_boost_init()
1826 regmap_write(pll->boost, BOOST_PLL_L_CON(1), in rockchip_boost_init()
1828 pll->boost_low_rate = rockchip_pll_con_to_rate(pll, con0, in rockchip_boost_init()
1830 pr_debug("boost-low-rate=%lu\n", pll->boost_low_rate); in rockchip_boost_init()
1835 regmap_write(pll->boost, BOOST_PLL_H_CON(0), in rockchip_boost_init()
1837 regmap_write(pll->boost, BOOST_PLL_H_CON(1), in rockchip_boost_init()
1839 pll->boost_high_rate = rockchip_pll_con_to_rate(pll, con0, in rockchip_boost_init()
1841 pr_debug("boost-high-rate=%lu\n", pll->boost_high_rate); in rockchip_boost_init()
1843 if (!of_property_read_u32(np, "rockchip,boost-backup-pll", &value)) { in rockchip_boost_init()
1844 pr_debug("boost-backup-pll=0x%x\n", value); in rockchip_boost_init()
1845 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_init()
1849 if (!of_property_read_u32(np, "rockchip,boost-backup-pll-usage", in rockchip_boost_init()
1850 &pll->boost_backup_pll_usage)) { in rockchip_boost_init()
1851 pr_debug("boost-backup-pll-usage=0x%x\n", in rockchip_boost_init()
1852 pll->boost_backup_pll_usage); in rockchip_boost_init()
1853 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_init()
1854 HIWORD_UPDATE(pll->boost_backup_pll_usage, in rockchip_boost_init()
1861 regmap_write(pll->boost, BOOST_SWITCH_THRESHOLD, value); in rockchip_boost_init()
1866 regmap_write(pll->boost, BOOST_STATIS_THRESHOLD, value); in rockchip_boost_init()
1871 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_init()
1877 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_init()
1881 pll->boost_enabled = true; in rockchip_boost_init()
1884 if (pll->boost_enabled) { in rockchip_boost_init()
1886 hlist_add_head(&pll->debug_node, &clk_boost_list); in rockchip_boost_init()
1894 struct rockchip_clk_pll *pll; in rockchip_boost_enable_recovery_sw_low() local
1899 pll = to_rockchip_clk_pll(hw); in rockchip_boost_enable_recovery_sw_low()
1900 if (!pll->boost_enabled) in rockchip_boost_enable_recovery_sw_low()
1903 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_enable_recovery_sw_low()
1907 regmap_read(pll->boost, BOOST_FSM_STATUS, &val); in rockchip_boost_enable_recovery_sw_low()
1910 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_enable_recovery_sw_low()
1917 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) in rockchip_boost_disable_low() argument
1919 if (!pll->boost_enabled) in rockchip_boost_disable_low()
1922 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_low()
1929 struct rockchip_clk_pll *pll; in rockchip_boost_disable_recovery_sw() local
1933 pll = to_rockchip_clk_pll(hw); in rockchip_boost_disable_recovery_sw()
1934 if (!pll->boost_enabled) in rockchip_boost_disable_recovery_sw()
1937 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_recovery_sw()
1940 regmap_write(pll->boost, BOOST_BOOST_CON, in rockchip_boost_disable_recovery_sw()
1947 struct rockchip_clk_pll *pll; in rockchip_boost_add_core_div() local
1952 pll = to_rockchip_clk_pll(hw); in rockchip_boost_add_core_div()
1953 if (!pll->boost_enabled || pll->boost_backup_pll_rate == prate) in rockchip_boost_add_core_div()
1957 if (pll->boost_backup_pll_usage == BOOST_BACKUP_PLL_USAGE_TARGET) in rockchip_boost_add_core_div()
1961 * low rate when change pll rate in boost module in rockchip_boost_add_core_div()
1963 if (pll->boost_low_rate && prate > pll->boost_low_rate) { in rockchip_boost_add_core_div()
1964 div = DIV_ROUND_UP(prate, pll->boost_low_rate) - 1; in rockchip_boost_add_core_div()
1965 regmap_write(pll->boost, BOOST_CLK_CON, in rockchip_boost_add_core_div()
1968 pll->boost_backup_pll_rate = prate; in rockchip_boost_add_core_div()
1978 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; in boost_summary_show() local
1987 seq_printf(s, " %s\n", clk_hw_get_name(&pll->hw)); in boost_summary_show()
1989 regmap_read(pll->boost, BOOST_SWITCH_CNT, &boost_count); in boost_summary_show()
1991 regmap_read(pll->boost, BOOST_HIGH_PERF_CNT0, &freq_cnt0); in boost_summary_show()
1992 regmap_read(pll->boost, BOOST_HIGH_PERF_CNT1, &freq_cnt1); in boost_summary_show()
1997 regmap_read(pll->boost, BOOST_SHORT_SWITCH_CNT, &short_count); in boost_summary_show()
1998 regmap_read(pll->boost, BOOST_STATIS_THRESHOLD, &short_threshold); in boost_summary_show()
1999 regmap_read(pll->boost, BOOST_SWITCH_THRESHOLD, &interval_time); in boost_summary_show()
2022 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; in boost_config_show() local
2024 seq_printf(s, "boost_enabled: %d\n", pll->boost_enabled); in boost_config_show()
2025 seq_printf(s, "boost_low_rate: %lu\n", pll->boost_low_rate); in boost_config_show()
2026 seq_printf(s, "boost_high_rate: %lu\n", pll->boost_high_rate); in boost_config_show()
2043 static int boost_debug_create_one(struct rockchip_clk_pll *pll, in boost_debug_create_one() argument
2048 pdentry = debugfs_lookup(clk_hw_get_name(&pll->hw), rootdir); in boost_debug_create_one()
2051 clk_hw_get_name(&pll->hw)); in boost_debug_create_one()
2056 pll, &boost_summary_fops); in boost_debug_create_one()
2063 pll, &boost_config_fops); in boost_debug_create_one()
2074 struct rockchip_clk_pll *pll; in boost_debug_init() local
2085 hlist_for_each_entry(pll, &clk_boost_list, debug_node) in boost_debug_init()
2086 boost_debug_create_one(pll, rootdir); in boost_debug_init()