158 	const u16 *control_regs;  member
202 		value = readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
207 		writeb(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
210 		readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
211 		barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
213 		value = readl(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
218 		writel(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
234 			priv->base + priv->control_regs[reg], bit);  in cpg_mstp_clock_endisable()
258 		value = readb(priv->base + priv->control_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
857 				readb(priv->base + priv->control_regs[reg]) :  in cpg_mssr_suspend_noirq()
858 				readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_suspend_noirq()
887 			oldval = readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
889 			oldval = readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
896 			writeb(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
898 			readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
899 			barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
902 			writel(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
971 		priv->control_regs = smstpcr;  in cpg_mssr_common_init()
975 		priv->control_regs = stbcr;  in cpg_mssr_common_init()
978 		priv->control_regs = mstpcr_for_v3u;  in cpg_mssr_common_init()