Lines Matching +full:0 +full:x1c000
22 .halt_reg = 0x1b004,
25 .enable_reg = 0x1b004,
26 .enable_mask = BIT(0),
35 .halt_reg = 0x22000,
38 .enable_reg = 0x22000,
39 .enable_mask = BIT(0),
48 .halt_reg = 0x1c000,
51 .enable_reg = 0x1c000,
52 .enable_mask = BIT(0),
61 .halt_reg = 0x22004,
64 .enable_reg = 0x22004,
65 .enable_mask = BIT(0),
74 .halt_reg = 0x1c004,
77 .enable_reg = 0x1c004,
78 .enable_mask = BIT(0),
87 .halt_reg = 0x6004,
90 .enable_reg = 0x6004,
91 .enable_mask = BIT(0),
101 .halt_reg = 0x8008,
104 .enable_reg = 0x8008,
105 .enable_mask = BIT(0),
130 [Q6SSTOP_BCR_RESET] = { 0x6000 },
168 if (ret < 0) { in q6sstopcc_qcs404_probe()
183 ret = qcom_cc_probe_by_index(pdev, 0, desc); in q6sstopcc_qcs404_probe()
187 return 0; in q6sstopcc_qcs404_probe()
203 return 0; in q6sstopcc_qcs404_remove()