Lines Matching +full:0 +full:x1004
31 { 249600000, 2000000000, 0 },
35 .l = 0x1a,
36 .alpha = 0xaaa,
37 .config_ctl_val = 0x20485699,
38 .config_ctl_hi_val = 0x00002267,
39 .config_ctl_hi1_val = 0x00000024,
40 .test_ctl_val = 0x00000000,
41 .test_ctl_hi_val = 0x00000002,
42 .test_ctl_hi1_val = 0x00000000,
43 .user_ctl_val = 0x00000000,
44 .user_ctl_hi_val = 0x00000805,
45 .user_ctl_hi1_val = 0x000000d0,
49 .offset = 0x100,
66 { P_BI_TCXO, 0 },
80 F(19200000, P_BI_TCXO, 1, 0, 0),
81 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
82 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
87 .cmd_rcgr = 0x1120,
88 .mnd_width = 0,
102 .halt_reg = 0x1078,
105 .enable_reg = 0x1078,
106 .enable_mask = BIT(0),
115 .halt_reg = 0x107c,
118 .enable_reg = 0x107c,
119 .enable_mask = BIT(0),
128 .halt_reg = 0x1088,
131 .enable_reg = 0x1088,
132 .enable_mask = BIT(0),
141 .halt_reg = 0x1098,
144 .enable_reg = 0x1098,
145 .enable_mask = BIT(0),
159 .halt_reg = 0x108c,
162 .enable_reg = 0x108c,
163 .enable_mask = BIT(0),
172 .halt_reg = 0x1004,
175 .enable_reg = 0x1004,
176 .enable_mask = BIT(0),
185 .halt_reg = 0x109c,
188 .enable_reg = 0x109c,
189 .enable_mask = BIT(0),
198 .halt_reg = 0x1064,
201 .enable_reg = 0x1064,
202 .enable_mask = BIT(0),
216 .gdscr = 0x106c,
217 .gds_hw_ctrl = 0x1540,
226 .gdscr = 0x100c,
227 .clamp_io_ctrl = 0x1508,
250 [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
251 [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
252 [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
253 [GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
254 [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
266 .max_register = 0x8008,