Lines Matching +full:0 +full:x6a000
58 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
89 { P_XO, 0 },
102 { P_XO, 0 },
115 { P_XO, 0 },
126 { P_USB3PHY_0_PIPE, 0 },
136 { P_USB3PHY_1_PIPE, 0 },
146 { P_PCIE20_PHY0_PIPE, 0 },
156 { P_PCIE20_PHY1_PIPE, 0 },
168 { P_XO, 0 },
182 { P_XO, 0 },
196 { P_XO, 0 },
209 { P_XO, 0 },
224 { P_XO, 0 },
238 { P_XO, 0 },
252 { P_XO, 0 },
267 { P_XO, 0 },
281 { P_XO, 0 },
297 { P_XO, 0 },
316 { P_XO, 0 },
337 { P_XO, 0 },
355 { P_XO, 0 },
371 { P_XO, 0 },
387 { P_XO, 0 },
395 .offset = 0x21000,
398 .enable_reg = 0x0b000,
399 .enable_mask = BIT(0),
426 .offset = 0x21000,
440 .offset = 0x4a000,
443 .enable_reg = 0x0b000,
458 .offset = 0x4a000,
473 .offset = 0x24000,
476 .enable_reg = 0x0b000,
491 .offset = 0x24000,
506 .offset = 0x37000,
510 .enable_reg = 0x0b000,
525 .offset = 0x37000,
554 .offset = 0x25000,
558 .enable_reg = 0x0b000,
572 .offset = 0x25000,
587 .offset = 0x22000,
590 .enable_reg = 0x0b000,
604 .offset = 0x22000,
619 F(19200000, P_XO, 1, 0, 0),
620 F(50000000, P_GPLL0, 16, 0, 0),
621 F(100000000, P_GPLL0, 8, 0, 0),
626 .cmd_rcgr = 0x27000,
654 .halt_reg = 0x30000,
656 .enable_reg = 0x30000,
671 F(19200000, P_XO, 1, 0, 0),
672 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
673 F(50000000, P_GPLL0, 16, 0, 0),
678 .cmd_rcgr = 0x0200c,
692 F(4800000, P_XO, 4, 0, 0),
693 F(9600000, P_XO, 2, 0, 0),
696 F(19200000, P_XO, 1, 0, 0),
698 F(50000000, P_GPLL0, 16, 0, 0),
703 .cmd_rcgr = 0x02024,
717 .cmd_rcgr = 0x03000,
730 .cmd_rcgr = 0x03014,
744 .cmd_rcgr = 0x04000,
757 .cmd_rcgr = 0x04014,
771 .cmd_rcgr = 0x05000,
784 .cmd_rcgr = 0x05014,
798 .cmd_rcgr = 0x06000,
811 .cmd_rcgr = 0x06014,
825 .cmd_rcgr = 0x07000,
838 .cmd_rcgr = 0x07014,
856 F(19200000, P_XO, 1, 0, 0),
872 .cmd_rcgr = 0x02044,
886 .cmd_rcgr = 0x03034,
900 .cmd_rcgr = 0x04034,
914 .cmd_rcgr = 0x05034,
928 .cmd_rcgr = 0x06034,
942 .cmd_rcgr = 0x07034,
961 F(19200000, P_XO, 1, 0, 0),
962 F(200000000, P_GPLL0, 4, 0, 0),
967 .cmd_rcgr = 0x75054,
980 F(19200000, P_XO, 1, 0, 0),
984 .cmd_rcgr = 0x75024,
998 .reg = 0x7501c,
1014 .cmd_rcgr = 0x76054,
1027 .cmd_rcgr = 0x76024,
1041 .reg = 0x7601c,
1061 F(96000000, P_GPLL2, 12, 0, 0),
1062 F(177777778, P_GPLL0, 4.5, 0, 0),
1063 F(192000000, P_GPLL2, 6, 0, 0),
1064 F(384000000, P_GPLL2, 3, 0, 0),
1069 .cmd_rcgr = 0x42004,
1083 F(19200000, P_XO, 1, 0, 0),
1084 F(160000000, P_GPLL0, 5, 0, 0),
1085 F(308570000, P_GPLL6, 3.5, 0, 0),
1089 .cmd_rcgr = 0x5d000,
1103 .cmd_rcgr = 0x43004,
1117 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1118 F(100000000, P_GPLL0, 8, 0, 0),
1119 F(133330000, P_GPLL0, 6, 0, 0),
1124 .cmd_rcgr = 0x3e00c,
1138 F(19200000, P_XO, 1, 0, 0),
1143 .cmd_rcgr = 0x3e05c,
1157 F(19200000, P_XO, 1, 0, 0),
1164 .cmd_rcgr = 0x3e020,
1178 .reg = 0x3e048,
1194 .cmd_rcgr = 0x3f00c,
1208 .cmd_rcgr = 0x3f05c,
1222 .cmd_rcgr = 0x3f020,
1236 .reg = 0x3f048,
1252 .halt_reg = 0x30018,
1254 .enable_reg = 0x30018,
1283 F(19200000, P_XO, 1, 0, 0),
1284 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1285 F(100000000, P_GPLL0, 8, 0, 0),
1286 F(133333333, P_GPLL0, 6, 0, 0),
1287 F(160000000, P_GPLL0, 5, 0, 0),
1288 F(200000000, P_GPLL0, 4, 0, 0),
1289 F(266666667, P_GPLL0, 3, 0, 0),
1294 .cmd_rcgr = 0x26004,
1322 F(19200000, P_XO, 1, 0, 0),
1323 F(200000000, P_GPLL0, 4, 0, 0),
1328 .cmd_rcgr = 0x68098,
1341 F(19200000, P_XO, 1, 0, 0),
1342 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1347 .cmd_rcgr = 0x68088,
1374 F(19200000, P_XO, 1, 0, 0),
1375 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1380 .cmd_rcgr = 0x68144,
1394 F(19200000, P_XO, 1, 0, 0),
1395 F(187200000, P_UBI32_PLL, 8, 0, 0),
1396 F(748800000, P_UBI32_PLL, 2, 0, 0),
1397 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1398 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1403 .cmd_rcgr = 0x68104,
1417 .reg = 0x68118,
1418 .shift = 0,
1434 .cmd_rcgr = 0x68124,
1448 .reg = 0x68138,
1449 .shift = 0,
1465 F(19200000, P_XO, 1, 0, 0),
1466 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1471 .cmd_rcgr = 0x68090,
1484 F(19200000, P_XO, 1, 0, 0),
1485 F(400000000, P_GPLL0, 2, 0, 0),
1490 .cmd_rcgr = 0x68158,
1503 F(19200000, P_XO, 1, 0, 0),
1504 F(300000000, P_BIAS_PLL, 1, 0, 0),
1509 .cmd_rcgr = 0x68080,
1536 F(19200000, P_XO, 1, 0, 0),
1537 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1538 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1543 .cmd_rcgr = 0x68020,
1556 .reg = 0x68400,
1557 .shift = 0,
1573 F(19200000, P_XO, 1, 0, 0),
1574 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1575 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1580 .cmd_rcgr = 0x68028,
1593 .reg = 0x68404,
1594 .shift = 0,
1610 .cmd_rcgr = 0x68030,
1623 .reg = 0x68410,
1624 .shift = 0,
1640 .cmd_rcgr = 0x68038,
1653 .reg = 0x68414,
1654 .shift = 0,
1670 .cmd_rcgr = 0x68040,
1683 .reg = 0x68420,
1684 .shift = 0,
1700 .cmd_rcgr = 0x68048,
1713 .reg = 0x68424,
1714 .shift = 0,
1730 .cmd_rcgr = 0x68050,
1743 .reg = 0x68430,
1744 .shift = 0,
1760 .cmd_rcgr = 0x68058,
1773 .reg = 0x68434,
1774 .shift = 0,
1790 F(19200000, P_XO, 1, 0, 0),
1791 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1792 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1793 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1794 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1795 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1796 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1797 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1802 .cmd_rcgr = 0x68060,
1815 .reg = 0x68440,
1816 .shift = 0,
1832 F(19200000, P_XO, 1, 0, 0),
1833 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1834 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1835 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1836 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1837 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1838 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1839 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1844 .cmd_rcgr = 0x68068,
1857 .reg = 0x68444,
1858 .shift = 0,
1874 F(19200000, P_XO, 1, 0, 0),
1875 F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1876 F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1877 F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1878 F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1879 F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1880 F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1881 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1886 .cmd_rcgr = 0x68070,
1899 .reg = 0x68450,
1900 .shift = 0,
1916 F(19200000, P_XO, 1, 0, 0),
1917 F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1918 F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919 F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1920 F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1921 F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1922 F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1923 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1928 .cmd_rcgr = 0x68078,
1941 .reg = 0x68454,
1942 .shift = 0,
1958 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1959 F(80000000, P_GPLL0, 10, 0, 0),
1960 F(100000000, P_GPLL0, 8, 0, 0),
1961 F(160000000, P_GPLL0, 5, 0, 0),
1966 .cmd_rcgr = 0x16004,
1979 F(19200000, P_XO, 1, 0, 0),
1984 .cmd_rcgr = 0x08004,
1998 .cmd_rcgr = 0x09004,
2012 .cmd_rcgr = 0x0a004,
2026 .halt_reg = 0x01008,
2028 .enable_reg = 0x01008,
2029 .enable_mask = BIT(0),
2043 .halt_reg = 0x02008,
2045 .enable_reg = 0x02008,
2046 .enable_mask = BIT(0),
2060 .halt_reg = 0x02004,
2062 .enable_reg = 0x02004,
2063 .enable_mask = BIT(0),
2077 .halt_reg = 0x03010,
2079 .enable_reg = 0x03010,
2080 .enable_mask = BIT(0),
2094 .halt_reg = 0x0300c,
2096 .enable_reg = 0x0300c,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0x04010,
2113 .enable_reg = 0x04010,
2114 .enable_mask = BIT(0),
2128 .halt_reg = 0x0400c,
2130 .enable_reg = 0x0400c,
2131 .enable_mask = BIT(0),
2145 .halt_reg = 0x05010,
2147 .enable_reg = 0x05010,
2148 .enable_mask = BIT(0),
2162 .halt_reg = 0x0500c,
2164 .enable_reg = 0x0500c,
2165 .enable_mask = BIT(0),
2179 .halt_reg = 0x06010,
2181 .enable_reg = 0x06010,
2182 .enable_mask = BIT(0),
2196 .halt_reg = 0x0600c,
2198 .enable_reg = 0x0600c,
2199 .enable_mask = BIT(0),
2213 .halt_reg = 0x07010,
2215 .enable_reg = 0x07010,
2216 .enable_mask = BIT(0),
2230 .halt_reg = 0x0700c,
2232 .enable_reg = 0x0700c,
2233 .enable_mask = BIT(0),
2247 .halt_reg = 0x0203c,
2249 .enable_reg = 0x0203c,
2250 .enable_mask = BIT(0),
2264 .halt_reg = 0x0302c,
2266 .enable_reg = 0x0302c,
2267 .enable_mask = BIT(0),
2281 .halt_reg = 0x0402c,
2283 .enable_reg = 0x0402c,
2284 .enable_mask = BIT(0),
2298 .halt_reg = 0x0502c,
2300 .enable_reg = 0x0502c,
2301 .enable_mask = BIT(0),
2315 .halt_reg = 0x0602c,
2317 .enable_reg = 0x0602c,
2318 .enable_mask = BIT(0),
2332 .halt_reg = 0x0702c,
2334 .enable_reg = 0x0702c,
2335 .enable_mask = BIT(0),
2349 .halt_reg = 0x13004,
2352 .enable_reg = 0x0b004,
2367 .halt_reg = 0x57024,
2369 .enable_reg = 0x57024,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x57020,
2386 .enable_reg = 0x57020,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x75010,
2403 .enable_reg = 0x75010,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x75014,
2420 .enable_reg = 0x75014,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x75008,
2437 .enable_reg = 0x75008,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x7500c,
2454 .enable_reg = 0x7500c,
2455 .enable_mask = BIT(0),
2469 .halt_reg = 0x75018,
2472 .enable_reg = 0x75018,
2473 .enable_mask = BIT(0),
2487 .halt_reg = 0x26048,
2489 .enable_reg = 0x26048,
2490 .enable_mask = BIT(0),
2504 .halt_reg = 0x76010,
2506 .enable_reg = 0x76010,
2507 .enable_mask = BIT(0),
2521 .halt_reg = 0x76014,
2523 .enable_reg = 0x76014,
2524 .enable_mask = BIT(0),
2538 .halt_reg = 0x76008,
2540 .enable_reg = 0x76008,
2541 .enable_mask = BIT(0),
2555 .halt_reg = 0x7600c,
2557 .enable_reg = 0x7600c,
2558 .enable_mask = BIT(0),
2572 .halt_reg = 0x76018,
2575 .enable_reg = 0x76018,
2576 .enable_mask = BIT(0),
2590 .halt_reg = 0x2604c,
2592 .enable_reg = 0x2604c,
2593 .enable_mask = BIT(0),
2607 .halt_reg = 0x3e044,
2609 .enable_reg = 0x3e044,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x26040,
2626 .enable_reg = 0x26040,
2627 .enable_mask = BIT(0),
2641 .halt_reg = 0x3e000,
2643 .enable_reg = 0x3e000,
2644 .enable_mask = BIT(0),
2658 .halt_reg = 0x3e008,
2660 .enable_reg = 0x3e008,
2661 .enable_mask = BIT(0),
2675 .halt_reg = 0x3e080,
2677 .enable_reg = 0x3e080,
2678 .enable_mask = BIT(0),
2692 .halt_reg = 0x3e040,
2695 .enable_reg = 0x3e040,
2696 .enable_mask = BIT(0),
2710 .halt_reg = 0x3e004,
2712 .enable_reg = 0x3e004,
2713 .enable_mask = BIT(0),
2727 .halt_reg = 0x3f044,
2729 .enable_reg = 0x3f044,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x26044,
2746 .enable_reg = 0x26044,
2747 .enable_mask = BIT(0),
2761 .halt_reg = 0x3f000,
2763 .enable_reg = 0x3f000,
2764 .enable_mask = BIT(0),
2778 .halt_reg = 0x3f008,
2780 .enable_reg = 0x3f008,
2781 .enable_mask = BIT(0),
2795 .halt_reg = 0x3f080,
2797 .enable_reg = 0x3f080,
2798 .enable_mask = BIT(0),
2812 .halt_reg = 0x3f040,
2815 .enable_reg = 0x3f040,
2816 .enable_mask = BIT(0),
2830 .halt_reg = 0x3f004,
2832 .enable_reg = 0x3f004,
2833 .enable_mask = BIT(0),
2847 .halt_reg = 0x4201c,
2849 .enable_reg = 0x4201c,
2850 .enable_mask = BIT(0),
2864 .halt_reg = 0x42018,
2866 .enable_reg = 0x42018,
2867 .enable_mask = BIT(0),
2881 .halt_reg = 0x5d014,
2883 .enable_reg = 0x5d014,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0x4301c,
2900 .enable_reg = 0x4301c,
2901 .enable_mask = BIT(0),
2915 .halt_reg = 0x43018,
2917 .enable_reg = 0x43018,
2918 .enable_mask = BIT(0),
2932 .halt_reg = 0x1d03c,
2934 .enable_reg = 0x1d03c,
2935 .enable_mask = BIT(0),
2949 .halt_reg = 0x68174,
2951 .enable_reg = 0x68174,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x68170,
2968 .enable_reg = 0x68170,
2969 .enable_mask = BIT(0),
2983 .halt_reg = 0x68160,
2985 .enable_reg = 0x68160,
2986 .enable_mask = BIT(0),
3000 .halt_reg = 0x68164,
3002 .enable_reg = 0x68164,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x68318,
3019 .enable_reg = 0x68318,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x6819c,
3036 .enable_reg = 0x6819c,
3037 .enable_mask = BIT(0),
3051 .halt_reg = 0x68198,
3053 .enable_reg = 0x68198,
3054 .enable_mask = BIT(0),
3068 .halt_reg = 0x68178,
3070 .enable_reg = 0x68178,
3071 .enable_mask = BIT(0),
3085 .halt_reg = 0x68168,
3087 .enable_reg = 0x68168,
3088 .enable_mask = BIT(0),
3102 .halt_reg = 0x6833c,
3104 .enable_reg = 0x6833c,
3105 .enable_mask = BIT(0),
3119 .halt_reg = 0x68194,
3121 .enable_reg = 0x68194,
3122 .enable_mask = BIT(0),
3136 .halt_reg = 0x68190,
3138 .enable_reg = 0x68190,
3139 .enable_mask = BIT(0),
3153 .halt_reg = 0x68338,
3155 .enable_reg = 0x68338,
3156 .enable_mask = BIT(0),
3170 .halt_reg = 0x6816c,
3172 .enable_reg = 0x6816c,
3173 .enable_mask = BIT(0),
3187 .halt_reg = 0x6830c,
3189 .enable_reg = 0x6830c,
3190 .enable_mask = BIT(0),
3204 .halt_reg = 0x68308,
3206 .enable_reg = 0x68308,
3207 .enable_mask = BIT(0),
3221 .halt_reg = 0x68314,
3223 .enable_reg = 0x68314,
3224 .enable_mask = BIT(0),
3238 .halt_reg = 0x68304,
3240 .enable_reg = 0x68304,
3241 .enable_mask = BIT(0),
3255 .halt_reg = 0x68300,
3257 .enable_reg = 0x68300,
3258 .enable_mask = BIT(0),
3272 .halt_reg = 0x68180,
3274 .enable_reg = 0x68180,
3275 .enable_mask = BIT(0),
3289 .halt_reg = 0x68188,
3291 .enable_reg = 0x68188,
3292 .enable_mask = BIT(0),
3306 .halt_reg = 0x68184,
3308 .enable_reg = 0x68184,
3309 .enable_mask = BIT(0),
3323 .halt_reg = 0x68270,
3325 .enable_reg = 0x68270,
3326 .enable_mask = BIT(0),
3340 .halt_reg = 0x68274,
3342 .enable_reg = 0x68274,
3343 .enable_mask = BIT(0),
3357 .halt_reg = 0x6820c,
3360 .enable_reg = 0x6820c,
3361 .enable_mask = BIT(0),
3375 .halt_reg = 0x68200,
3378 .enable_reg = 0x68200,
3379 .enable_mask = BIT(0),
3393 .halt_reg = 0x68204,
3396 .enable_reg = 0x68204,
3397 .enable_mask = BIT(0),
3411 .halt_reg = 0x68210,
3414 .enable_reg = 0x68210,
3415 .enable_mask = BIT(0),
3429 .halt_reg = 0x68208,
3432 .enable_reg = 0x68208,
3433 .enable_mask = BIT(0),
3447 .halt_reg = 0x6822c,
3450 .enable_reg = 0x6822c,
3451 .enable_mask = BIT(0),
3465 .halt_reg = 0x68220,
3468 .enable_reg = 0x68220,
3469 .enable_mask = BIT(0),
3483 .halt_reg = 0x68224,
3486 .enable_reg = 0x68224,
3487 .enable_mask = BIT(0),
3501 .halt_reg = 0x68230,
3504 .enable_reg = 0x68230,
3505 .enable_mask = BIT(0),
3519 .halt_reg = 0x68228,
3522 .enable_reg = 0x68228,
3523 .enable_mask = BIT(0),
3537 .halt_reg = 0x56308,
3539 .enable_reg = 0x56308,
3540 .enable_mask = BIT(0),
3554 .halt_reg = 0x5630c,
3556 .enable_reg = 0x5630c,
3557 .enable_mask = BIT(0),
3571 .halt_reg = 0x58004,
3573 .enable_reg = 0x58004,
3574 .enable_mask = BIT(0),
3588 .halt_reg = 0x56008,
3590 .enable_reg = 0x56008,
3591 .enable_mask = BIT(0),
3605 .halt_reg = 0x5600c,
3607 .enable_reg = 0x5600c,
3608 .enable_mask = BIT(0),
3622 .halt_reg = 0x56108,
3624 .enable_reg = 0x56108,
3625 .enable_mask = BIT(0),
3639 .halt_reg = 0x5610c,
3641 .enable_reg = 0x5610c,
3642 .enable_mask = BIT(0),
3656 .halt_reg = 0x56208,
3658 .enable_reg = 0x56208,
3659 .enable_mask = BIT(0),
3673 .halt_reg = 0x5620c,
3675 .enable_reg = 0x5620c,
3676 .enable_mask = BIT(0),
3690 .halt_reg = 0x68240,
3692 .enable_reg = 0x68240,
3693 .enable_mask = BIT(0),
3707 .halt_reg = 0x68244,
3709 .enable_reg = 0x68244,
3710 .enable_mask = BIT(0),
3724 .halt_reg = 0x68248,
3726 .enable_reg = 0x68248,
3727 .enable_mask = BIT(0),
3741 .halt_reg = 0x6824c,
3743 .enable_reg = 0x6824c,
3744 .enable_mask = BIT(0),
3758 .halt_reg = 0x68250,
3760 .enable_reg = 0x68250,
3761 .enable_mask = BIT(0),
3775 .halt_reg = 0x68254,
3777 .enable_reg = 0x68254,
3778 .enable_mask = BIT(0),
3792 .halt_reg = 0x68258,
3794 .enable_reg = 0x68258,
3795 .enable_mask = BIT(0),
3809 .halt_reg = 0x6825c,
3811 .enable_reg = 0x6825c,
3812 .enable_mask = BIT(0),
3826 .halt_reg = 0x68260,
3828 .enable_reg = 0x68260,
3829 .enable_mask = BIT(0),
3843 .halt_reg = 0x68264,
3845 .enable_reg = 0x68264,
3846 .enable_mask = BIT(0),
3860 .halt_reg = 0x68268,
3862 .enable_reg = 0x68268,
3863 .enable_mask = BIT(0),
3877 .halt_reg = 0x6826c,
3879 .enable_reg = 0x6826c,
3880 .enable_mask = BIT(0),
3894 .halt_reg = 0x68320,
3896 .enable_reg = 0x68320,
3897 .enable_mask = BIT(0),
3911 .halt_reg = 0x68324,
3913 .enable_reg = 0x68324,
3914 .enable_mask = BIT(0),
3928 .halt_reg = 0x68328,
3930 .enable_reg = 0x68328,
3931 .enable_mask = BIT(0),
3945 .halt_reg = 0x6832c,
3947 .enable_reg = 0x6832c,
3948 .enable_mask = BIT(0),
3962 .halt_reg = 0x68330,
3964 .enable_reg = 0x68330,
3965 .enable_mask = BIT(0),
3979 .halt_reg = 0x68334,
3981 .enable_reg = 0x68334,
3982 .enable_mask = BIT(0),
3996 .halt_reg = 0x56010,
3998 .enable_reg = 0x56010,
3999 .enable_mask = BIT(0),
4013 .halt_reg = 0x56014,
4015 .enable_reg = 0x56014,
4016 .enable_mask = BIT(0),
4030 .halt_reg = 0x56018,
4032 .enable_reg = 0x56018,
4033 .enable_mask = BIT(0),
4047 .halt_reg = 0x5601c,
4049 .enable_reg = 0x5601c,
4050 .enable_mask = BIT(0),
4064 .halt_reg = 0x56020,
4066 .enable_reg = 0x56020,
4067 .enable_mask = BIT(0),
4081 .halt_reg = 0x56024,
4083 .enable_reg = 0x56024,
4084 .enable_mask = BIT(0),
4098 .halt_reg = 0x56028,
4100 .enable_reg = 0x56028,
4101 .enable_mask = BIT(0),
4115 .halt_reg = 0x5602c,
4117 .enable_reg = 0x5602c,
4118 .enable_mask = BIT(0),
4132 .halt_reg = 0x56030,
4134 .enable_reg = 0x56030,
4135 .enable_mask = BIT(0),
4149 .halt_reg = 0x56034,
4151 .enable_reg = 0x56034,
4152 .enable_mask = BIT(0),
4166 .halt_reg = 0x56110,
4168 .enable_reg = 0x56110,
4169 .enable_mask = BIT(0),
4183 .halt_reg = 0x56114,
4185 .enable_reg = 0x56114,
4186 .enable_mask = BIT(0),
4200 .halt_reg = 0x56210,
4202 .enable_reg = 0x56210,
4203 .enable_mask = BIT(0),
4217 .halt_reg = 0x56214,
4219 .enable_reg = 0x56214,
4220 .enable_mask = BIT(0),
4234 .halt_reg = 0x16024,
4237 .enable_reg = 0x0b004,
4238 .enable_mask = BIT(0),
4252 .halt_reg = 0x16020,
4255 .enable_reg = 0x0b004,
4270 .halt_reg = 0x1601c,
4273 .enable_reg = 0x0b004,
4288 .halt_reg = 0x08000,
4290 .enable_reg = 0x08000,
4291 .enable_mask = BIT(0),
4305 .halt_reg = 0x09000,
4307 .enable_reg = 0x09000,
4308 .enable_mask = BIT(0),
4322 .halt_reg = 0x0a000,
4324 .enable_reg = 0x0a000,
4325 .enable_mask = BIT(0),
4339 F(19200000, P_XO, 1, 0, 0),
4340 F(100000000, P_GPLL0, 8, 0, 0),
4345 .cmd_rcgr = 0x75070,
4358 .halt_reg = 0x75070,
4361 .enable_reg = 0x75070,
4376 .halt_reg = 0x75048,
4379 .enable_reg = 0x75048,
4380 .enable_mask = BIT(0),
4394 .l = 0x4e,
4395 .config_ctl_val = 0x200d4aa8,
4396 .config_ctl_hi_val = 0x3c2,
4397 .main_output_mask = BIT(0),
4399 .pre_div_val = 0x0,
4401 .post_div_val = 0x0,
4406 .l = 0x3e,
4407 .alpha = 0x0,
4408 .alpha_hi = 0x80,
4409 .config_ctl_val = 0x4001055b,
4410 .main_output_mask = BIT(0),
4411 .pre_div_val = 0x0,
4413 .post_div_val = 0x1 << 8,
4416 .vco_val = 0x0,
4661 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4662 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4663 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4664 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4665 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4666 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4667 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4668 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4669 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4670 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4671 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4672 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4673 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4674 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4675 [GCC_SMMU_BCR] = { 0x12000, 0 },
4676 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4677 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4678 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4679 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4680 [GCC_PRNG_BCR] = { 0x13000, 0 },
4681 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4682 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4683 [GCC_WCSS_BCR] = { 0x18000, 0 },
4684 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4685 [GCC_NSS_BCR] = { 0x19000, 0 },
4686 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4687 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4688 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4689 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4690 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4691 [GCC_TCSR_BCR] = { 0x28000, 0 },
4692 [GCC_QDSS_BCR] = { 0x29000, 0 },
4693 [GCC_DCD_BCR] = { 0x2a000, 0 },
4694 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4695 [GCC_MPM_BCR] = { 0x2c000, 0 },
4696 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4697 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4698 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4699 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4700 [GCC_TLMM_BCR] = { 0x34000, 0 },
4701 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4702 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4703 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4704 [GCC_USB0_BCR] = { 0x3e070, 0 },
4705 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4706 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4707 [GCC_USB1_BCR] = { 0x3f070, 0 },
4708 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4709 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4710 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4711 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4712 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4713 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4714 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4715 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4716 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4717 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4718 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4719 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4720 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4721 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4722 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4723 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4724 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4725 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4726 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4727 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4728 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4729 [GCC_QPIC_BCR] = { 0x57018, 0 },
4730 [GCC_MDIO_BCR] = { 0x58000, 0 },
4731 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4732 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4733 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4734 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4735 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4736 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4737 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4738 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4739 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4740 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4741 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4742 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4743 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4744 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4745 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4746 [GCC_DCC_BCR] = { 0x77000, 0 },
4747 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4748 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4749 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4750 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4751 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4752 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4753 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4754 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4755 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4756 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4757 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4758 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4759 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4760 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4761 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4762 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4763 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4764 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4765 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4766 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4767 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4768 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4769 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4770 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4771 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4772 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4773 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4774 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4775 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4776 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4777 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4778 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4779 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4780 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4781 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4782 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4783 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4784 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4785 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4786 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4787 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4788 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4789 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4790 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4791 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4792 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4805 .max_register = 0x7fffc,
4828 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq8074_probe()