45 #define RCG_CFG_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)  argument
46 #define RCG_M_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)  argument
47 #define RCG_N_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)  argument
48 #define RCG_D_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)  argument
65 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_is_enabled()  local
69 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in clk_rcg2_is_enabled()
78 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_get_parent()  local
83 	ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);  in clk_rcg2_get_parent()
91 		if (cfg == rcg->parent_map[i].cfg)  in clk_rcg2_get_parent()
100 static int update_config(struct clk_rcg2 *rcg)  in update_config()  argument
104 	struct clk_hw *hw = &rcg->clkr.hw;  in update_config()
107 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in update_config()
114 		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in update_config()
128 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_parent()  local
130 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_set_parent()
132 	ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),  in clk_rcg2_set_parent()
137 	return update_config(rcg);  in clk_rcg2_set_parent()
168 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_recalc_rate()  local
171 	regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);  in clk_rcg2_recalc_rate()
173 	if (rcg->mnd_width) {  in clk_rcg2_recalc_rate()
174 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_recalc_rate()
175 		regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);  in clk_rcg2_recalc_rate()
177 		regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);  in clk_rcg2_recalc_rate()
185 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_recalc_rate()
198 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in _freq_tbl_determine_rate()  local
215 	index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in _freq_tbl_determine_rate()
252 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_rate()  local
254 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);  in clk_rcg2_determine_rate()
260 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_floor_rate()  local
262 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);  in clk_rcg2_determine_floor_rate()
265 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in __clk_rcg2_configure()  argument
268 	struct clk_hw *hw = &rcg->clkr.hw;  in __clk_rcg2_configure()
269 	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in __clk_rcg2_configure()
274 	if (rcg->mnd_width && f->n) {  in __clk_rcg2_configure()
275 		mask = BIT(rcg->mnd_width) - 1;  in __clk_rcg2_configure()
276 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
277 				RCG_M_OFFSET(rcg), mask, f->m);  in __clk_rcg2_configure()
281 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
282 				RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));  in __clk_rcg2_configure()
295 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
296 				RCG_D_OFFSET(rcg), mask, not2d_val);  in __clk_rcg2_configure()
301 	mask = BIT(rcg->hid_width) - 1;  in __clk_rcg2_configure()
304 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in __clk_rcg2_configure()
305 	if (rcg->mnd_width && f->n && (f->m != f->n))  in __clk_rcg2_configure()
307 	return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),  in __clk_rcg2_configure()
311 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in clk_rcg2_configure()  argument
315 	ret = __clk_rcg2_configure(rcg, f);  in clk_rcg2_configure()
319 	return update_config(rcg);  in clk_rcg2_configure()
325 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in __clk_rcg2_set_rate()  local
330 		f = qcom_find_freq_floor(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
333 		f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
342 	return clk_rcg2_configure(rcg, f);  in __clk_rcg2_set_rate()
421 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_set_rate()  local
422 	struct freq_tbl f = *rcg->freq_tbl;  in clk_edp_pixel_set_rate()
427 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_set_rate()
443 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_set_rate()
451 		return clk_rcg2_configure(rcg, &f);  in clk_edp_pixel_set_rate()
467 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_determine_rate()  local
468 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_edp_pixel_determine_rate()
472 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_determine_rate()
474 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_edp_pixel_determine_rate()
493 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_determine_rate()
521 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_determine_rate()  local
522 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_byte_determine_rate()
523 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_byte_determine_rate()
525 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_determine_rate()
545 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_set_rate()  local
546 	struct freq_tbl f = *rcg->freq_tbl;  in clk_byte_set_rate()
548 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_set_rate()
555 	return clk_rcg2_configure(rcg, &f);  in clk_byte_set_rate()
579 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_determine_rate()  local
581 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_determine_rate()
602 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_set_rate()  local
606 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_set_rate()
614 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_byte2_set_rate()
619 		if (cfg == rcg->parent_map[i].cfg) {  in clk_byte2_set_rate()
620 			f.src = rcg->parent_map[i].src;  in clk_byte2_set_rate()
621 			return clk_rcg2_configure(rcg, &f);  in clk_byte2_set_rate()
681 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_pixel_set_rate()  local
686 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_pixel_set_rate()
690 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_pixel_set_rate()
695 		if (cfg == rcg->parent_map[i].cfg) {  in clk_pixel_set_rate()
696 			f.src = rcg->parent_map[i].src;  in clk_pixel_set_rate()
707 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_pixel_set_rate()
715 		return clk_rcg2_configure(rcg, &f);  in clk_pixel_set_rate()
789 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_gfx3d_set_rate_and_parent()  local
794 	cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_gfx3d_set_rate_and_parent()
795 	ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);  in clk_gfx3d_set_rate_and_parent()
799 	return update_config(rcg);  in clk_gfx3d_set_rate_and_parent()
826 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_force_enable()  local
830 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_set_force_enable()
849 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_clear_force_enable()  local
851 	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_clear_force_enable()
858 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_force_enable_clear()  local
865 	ret = clk_rcg2_configure(rcg, f);  in clk_rcg2_shared_force_enable_clear()
875 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_set_rate()  local
878 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg2_shared_set_rate()
887 		return __clk_rcg2_configure(rcg, f);  in clk_rcg2_shared_set_rate()
900 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_enable()  local
911 	ret = update_config(rcg);  in clk_rcg2_shared_enable()
920 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_disable()  local
927 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_shared_disable()
939 	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_rcg2_shared_disable()
940 		     rcg->safe_src_index << CFG_SRC_SEL_SHIFT);  in clk_rcg2_shared_disable()
942 	update_config(rcg);  in clk_rcg2_shared_disable()
947 	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);  in clk_rcg2_shared_disable()
966 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_dfs_populate_freq()  local
972 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);  in clk_rcg2_dfs_populate_freq()
974 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_dfs_populate_freq()
984 		if (src == rcg->parent_map[i].cfg) {  in clk_rcg2_dfs_populate_freq()
985 			f->src = rcg->parent_map[i].src;  in clk_rcg2_dfs_populate_freq()
986 			p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);  in clk_rcg2_dfs_populate_freq()
994 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_dfs_populate_freq()
995 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),  in clk_rcg2_dfs_populate_freq()
1000 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),  in clk_rcg2_dfs_populate_freq()
1011 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)  in clk_rcg2_dfs_populate_freq_table()  argument
1020 	rcg->freq_tbl = freq_tbl;  in clk_rcg2_dfs_populate_freq_table()
1023 		clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);  in clk_rcg2_dfs_populate_freq_table()
1031 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_dfs_determine_rate()  local
1034 	if (!rcg->freq_tbl) {  in clk_rcg2_dfs_determine_rate()
1035 		ret = clk_rcg2_dfs_populate_freq_table(rcg);  in clk_rcg2_dfs_determine_rate()
1049 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_dfs_recalc_rate()  local
1052 	regmap_read(rcg->clkr.regmap,  in clk_rcg2_dfs_recalc_rate()
1053 		    rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);  in clk_rcg2_dfs_recalc_rate()
1057 	if (rcg->freq_tbl)  in clk_rcg2_dfs_recalc_rate()
1058 		return rcg->freq_tbl[level].freq;  in clk_rcg2_dfs_recalc_rate()
1067 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),  in clk_rcg2_dfs_recalc_rate()
1070 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_dfs_recalc_rate()
1078 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_dfs_recalc_rate()
1079 		regmap_read(rcg->clkr.regmap,  in clk_rcg2_dfs_recalc_rate()
1080 			    rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);  in clk_rcg2_dfs_recalc_rate()
1083 		regmap_read(rcg->clkr.regmap,  in clk_rcg2_dfs_recalc_rate()
1084 			    rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);  in clk_rcg2_dfs_recalc_rate()
1103 	struct clk_rcg2 *rcg = data->rcg;  in clk_rcg2_enable_dfs()  local
1108 	ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);  in clk_rcg2_enable_dfs()
1122 	rcg->freq_tbl = NULL;  in clk_rcg2_enable_dfs()
1145 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_dp_set_rate()  local
1147 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_dp_set_rate()
1153 			GENMASK(rcg->mnd_width - 1, 0),  in clk_rcg2_dp_set_rate()
1154 			GENMASK(rcg->mnd_width - 1, 0), &den, &num);  in clk_rcg2_dp_set_rate()
1159 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_dp_set_rate()
1165 		if (cfg == rcg->parent_map[i].cfg) {  in clk_rcg2_dp_set_rate()
1166 			f.src = rcg->parent_map[i].src;  in clk_rcg2_dp_set_rate()
1183 	return clk_rcg2_configure(rcg, &f);  in clk_rcg2_dp_set_rate()
1195 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_dp_determine_rate()  local
1201 			GENMASK(rcg->mnd_width - 1, 0),  in clk_rcg2_dp_determine_rate()
1202 			GENMASK(rcg->mnd_width - 1, 0), &den, &num);  in clk_rcg2_dp_determine_rate()