70 static const char *uart_parent[] = {"uart_pll", "vctcxo"};
71 static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
74 static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
80 	struct clk *vctcxo;  in mmp2_clk_init()  local
106 	vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);  in mmp2_clk_init()
107 	clk_register_clkdev(vctcxo, "vctcxo", NULL);  in mmp2_clk_init()
178 	clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",  in mmp2_clk_init()
193 	clk = mmp_clk_register_apbc("twsi0", "vctcxo",  in mmp2_clk_init()
197 	clk = mmp_clk_register_apbc("twsi1", "vctcxo",  in mmp2_clk_init()
201 	clk = mmp_clk_register_apbc("twsi2", "vctcxo",  in mmp2_clk_init()
205 	clk = mmp_clk_register_apbc("twsi3", "vctcxo",  in mmp2_clk_init()
209 	clk = mmp_clk_register_apbc("twsi4", "vctcxo",  in mmp2_clk_init()
213 	clk = mmp_clk_register_apbc("twsi5", "vctcxo",  in mmp2_clk_init()
217 	clk = mmp_clk_register_apbc("gpio", "vctcxo",  in mmp2_clk_init()
229 	clk = mmp_clk_register_apbc("pwm0", "vctcxo",  in mmp2_clk_init()
233 	clk = mmp_clk_register_apbc("pwm1", "vctcxo",  in mmp2_clk_init()
237 	clk = mmp_clk_register_apbc("pwm2", "vctcxo",  in mmp2_clk_init()
241 	clk = mmp_clk_register_apbc("pwm3", "vctcxo",  in mmp2_clk_init()
249 	clk_set_parent(clk, vctcxo);  in mmp2_clk_init()
260 	clk_set_parent(clk, vctcxo);  in mmp2_clk_init()
271 	clk_set_parent(clk, vctcxo);  in mmp2_clk_init()
282 	clk_set_parent(clk, vctcxo);  in mmp2_clk_init()
398 	clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",  in mmp2_clk_init()