clk/meson/axg.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
27 	.data = &(struct meson_clk_pll_data){
31 			.width   = 1,
36 			.width   = 9,
41 			.width   = 5,
46 			.width   = 12,
51 			.width   = 1,
56 			.width   = 1,
70 	.data = &(struct clk_regmap_div_data){
73 		.width = 2,
91 	.data = &(struct meson_clk_pll_data){
95 			.width   = 1,
100 			.width   = 9,
105 			.width   = 5,
110 			.width   = 1,
115 			.width   = 1,
129 	.data = &(struct clk_regmap_div_data){
132 		.width = 2,
188 	.data = &(struct meson_clk_pll_data){
192 			.width   = 1,
197 			.width   = 9,
202 			.width   = 5,
207 			.width   = 10,
212 			.width   = 1,
217 			.width   = 1,
234 	.data = &(struct clk_regmap_div_data){
237 		.width = 2,
260 	.data = &(struct meson_clk_pll_data){
264 			.width   = 1,
269 			.width   = 9,
274 			.width   = 5,
279 			.width   = 13,
284 			.width   = 1,
289 			.width   = 1,
307 	.data = &(struct clk_regmap_div_data){
310 		.width = 2,
336 	.data = &(struct clk_regmap_gate_data){
363 	.data = &(struct clk_regmap_gate_data){
382 		 * b) CCF has a clock hand-off mechanism to make the sure the
401 	.data = &(struct clk_regmap_gate_data){
427 	.data = &(struct clk_regmap_gate_data){
455 	.data = &(struct clk_regmap_gate_data){
470 	.data = &(struct clk_regmap_div_data){
473 		.width = 1,
486 	.data = &(struct meson_clk_mpll_data){
490 			.width   = 14,
495 			.width	 = 1,
500 			.width   = 9,
505 			.width	 = 1,
521 	.data = &(struct clk_regmap_gate_data){
537 	.data = &(struct meson_clk_mpll_data){
541 			.width   = 14,
546 			.width	 = 1,
551 			.width   = 9,
556 			.width	 = 1,
572 	.data = &(struct clk_regmap_gate_data){
588 	.data = &(struct meson_clk_mpll_data){
592 			.width   = 14,
597 			.width	 = 1,
602 			.width   = 9,
607 			.width	 = 1,
612 			.width	 = 1,
628 	.data = &(struct clk_regmap_gate_data){
644 	.data = &(struct meson_clk_mpll_data){
648 			.width   = 14,
653 			.width	 = 1,
658 			.width   = 9,
663 			.width	 = 1,
679 	.data = &(struct clk_regmap_gate_data){
713 	.data = &(struct meson_clk_pll_data){
717 			.width   = 1,
722 			.width   = 9,
727 			.width   = 5,
732 			.width   = 12,
737 			.width   = 1,
742 			.width   = 1,
759 	.data = &(struct clk_regmap_div_data){
762 		.width = 2,
777 	.data = &(struct clk_regmap_div_data){
780 		.width = 2,
795 	.data = &(struct clk_regmap_mux_data){
812 	.data = &(struct clk_regmap_mux_data){
829 	.data = &(struct clk_regmap_gate_data){
844 	.data = &(struct clk_regmap_gate_data){
869 	.data = &(struct clk_regmap_mux_data){
884 	.data = &(struct clk_regmap_div_data){
887 		.width = 7,
901 	.data = &(struct clk_regmap_gate_data){
932 	.data = &(struct clk_regmap_mux_data){
947 	.data = &(struct clk_regmap_div_data){
950 		.width = 7,
965 	.data = &(struct clk_regmap_gate_data){
982 	.data = &(struct clk_regmap_mux_data){
997 	.data = &(struct clk_regmap_div_data){
1000 		.width = 7,
1015 	.data = &(struct clk_regmap_gate_data){
1047 	.data = &(struct clk_regmap_mux_data){
1068 	.data = &(struct clk_regmap_div_data){
1071 		.width = 11,
1085 	.data = &(struct clk_regmap_gate_data){
1355 	{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
1363 		.name	= "axg-clkc",