1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "clk-mtk.h"
16 #define REG_CON0		0
19 #define CON0_BASE_EN		BIT(0)
20 #define CON0_PWR_ON		BIT(0)
26 #define POSTDIV_MASK		0x7
33  * a divider in the PLL feedback loop which consists of 7 bits for the integer
35  * have a 3 bit power-of-two post divider.
57 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_is_prepared()  local
59 	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;  in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,  in __mtk_pll_recalc_rate()  argument
65 	int pcwbits = pll->data->pcwbits;  in __mtk_pll_recalc_rate()
66 	int pcwfbits = 0;  in __mtk_pll_recalc_rate()
69 	u8 c = 0;  in __mtk_pll_recalc_rate()
71 	/* The fractional part of the PLL divider. */  in __mtk_pll_recalc_rate()
72 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in __mtk_pll_recalc_rate()
74 		pcwfbits = pcwbits - ibits;  in __mtk_pll_recalc_rate()
78 	if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))  in __mtk_pll_recalc_rate()
86 	return ((unsigned long)vco + postdiv - 1) / postdiv;  in __mtk_pll_recalc_rate()
89 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_enable()  argument
93 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_enable()
94 		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_enable()
95 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_enable()
96 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_enable()
97 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;  in __mtk_pll_tuner_enable()
98 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_enable()
102 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_disable()  argument
106 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_disable()
107 		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_disable()
108 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_disable()
109 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_disable()
110 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;  in __mtk_pll_tuner_disable()
111 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_disable()
115 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,  in mtk_pll_set_rate_regs()  argument
121 	__mtk_pll_tuner_disable(pll);  in mtk_pll_set_rate_regs()
124 	val = readl(pll->pd_addr);  in mtk_pll_set_rate_regs()
125 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);  in mtk_pll_set_rate_regs()
126 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;  in mtk_pll_set_rate_regs()
129 	if (pll->pd_addr != pll->pcw_addr) {  in mtk_pll_set_rate_regs()
130 		writel(val, pll->pd_addr);  in mtk_pll_set_rate_regs()
131 		val = readl(pll->pcw_addr);  in mtk_pll_set_rate_regs()
135 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,  in mtk_pll_set_rate_regs()
136 			pll->data->pcw_shift);  in mtk_pll_set_rate_regs()
137 	val |= pcw << pll->data->pcw_shift;  in mtk_pll_set_rate_regs()
138 	writel(val, pll->pcw_addr);  in mtk_pll_set_rate_regs()
139 	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;  in mtk_pll_set_rate_regs()
140 	writel(chg, pll->pcw_chg_addr);  in mtk_pll_set_rate_regs()
141 	if (pll->tuner_addr)  in mtk_pll_set_rate_regs()
142 		writel(val + 1, pll->tuner_addr);  in mtk_pll_set_rate_regs()
145 	__mtk_pll_tuner_enable(pll);  in mtk_pll_set_rate_regs()
151  * mtk_pll_calc_values - calculate good values for a given input frequency.
152  * @pll:	The pll
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,  in mtk_pll_calc_values()  argument
162 	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);  in mtk_pll_calc_values()
163 	const struct mtk_pll_div_table *div_table = pll->data->div_table;  in mtk_pll_calc_values()
168 	if (freq > pll->data->fmax)  in mtk_pll_calc_values()
169 		freq = pll->data->fmax;  in mtk_pll_calc_values()
172 		if (freq > div_table[0].freq)  in mtk_pll_calc_values()
173 			freq = div_table[0].freq;  in mtk_pll_calc_values()
175 		for (val = 0; div_table[val + 1].freq != 0; val++) {  in mtk_pll_calc_values()
181 		for (val = 0; val < 5; val++) {  in mtk_pll_calc_values()
189 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in mtk_pll_calc_values()
190 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);  in mtk_pll_calc_values()
199 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_set_rate()  local
200 	u32 pcw = 0;  in mtk_pll_set_rate()
203 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);  in mtk_pll_set_rate()
204 	mtk_pll_set_rate_regs(pll, pcw, postdiv);  in mtk_pll_set_rate()
206 	return 0;  in mtk_pll_set_rate()
212 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_recalc_rate()  local
216 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;  in mtk_pll_recalc_rate()
219 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;  in mtk_pll_recalc_rate()
220 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);  in mtk_pll_recalc_rate()
222 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);  in mtk_pll_recalc_rate()
228 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_round_rate()  local
229 	u32 pcw = 0;  in mtk_pll_round_rate()
232 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);  in mtk_pll_round_rate()
234 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);  in mtk_pll_round_rate()
239 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare()  local
242 	r = readl(pll->pwr_addr) | CON0_PWR_ON;  in mtk_pll_prepare()
243 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
246 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;  in mtk_pll_prepare()
247 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
250 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
251 	r |= pll->data->en_mask;  in mtk_pll_prepare()
252 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
254 	__mtk_pll_tuner_enable(pll);  in mtk_pll_prepare()
258 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_prepare()
259 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
260 		r |= pll->data->rst_bar_mask;  in mtk_pll_prepare()
261 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
264 	return 0;  in mtk_pll_prepare()
269 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare()  local
272 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_unprepare()
273 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
274 		r &= ~pll->data->rst_bar_mask;  in mtk_pll_unprepare()
275 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
278 	__mtk_pll_tuner_disable(pll);  in mtk_pll_unprepare()
280 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
282 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
284 	r = readl(pll->pwr_addr) | CON0_ISO_EN;  in mtk_pll_unprepare()
285 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
287 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;  in mtk_pll_unprepare()
288 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
303 	struct mtk_clk_pll *pll;  in mtk_clk_register_pll()  local
308 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mtk_clk_register_pll()
309 	if (!pll)  in mtk_clk_register_pll()
310 		return ERR_PTR(-ENOMEM);  in mtk_clk_register_pll()
312 	pll->base_addr = base + data->reg;  in mtk_clk_register_pll()
313 	pll->pwr_addr = base + data->pwr_reg;  in mtk_clk_register_pll()
314 	pll->pd_addr = base + data->pd_reg;  in mtk_clk_register_pll()
315 	pll->pcw_addr = base + data->pcw_reg;  in mtk_clk_register_pll()
316 	if (data->pcw_chg_reg)  in mtk_clk_register_pll()
317 		pll->pcw_chg_addr = base + data->pcw_chg_reg;  in mtk_clk_register_pll()
319 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;  in mtk_clk_register_pll()
320 	if (data->tuner_reg)  in mtk_clk_register_pll()
321 		pll->tuner_addr = base + data->tuner_reg;  in mtk_clk_register_pll()
322 	if (data->tuner_en_reg)  in mtk_clk_register_pll()
323 		pll->tuner_en_addr = base + data->tuner_en_reg;  in mtk_clk_register_pll()
324 	pll->hw.init = &init;  in mtk_clk_register_pll()
325 	pll->data = data;  in mtk_clk_register_pll()
327 	init.name = data->name;  in mtk_clk_register_pll()
328 	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;  in mtk_clk_register_pll()
330 	if (data->parent_name)  in mtk_clk_register_pll()
331 		init.parent_names = &data->parent_name;  in mtk_clk_register_pll()
336 	clk = clk_register(NULL, &pll->hw);  in mtk_clk_register_pll()
339 		kfree(pll);  in mtk_clk_register_pll()
351 	base = of_iomap(node, 0);  in mtk_clk_register_plls()
357 	for (i = 0; i < num_plls; i++) {  in mtk_clk_register_plls()
358 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
360 		clk = mtk_clk_register_pll(pll, base);  in mtk_clk_register_plls()
364 					pll->name, PTR_ERR(clk));  in mtk_clk_register_plls()
368 		clk_data->clks[pll->id] = clk;  in mtk_clk_register_plls()