clk/mediatek/clk-mt8516.c

536 #define GATE_TOP2(_id, _name, _parent, _shift) {	\  macro
614 	GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
615 	GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
616 	GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
617 	GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
618 	GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
619 	GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
620 	GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
621 	GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
622 	GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
623 	GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
624 	GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
625 	GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
626 	GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
627 	GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
628 	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
630 	GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
631 	GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
632 	GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
633 	GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
634 	GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
635 	GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
636 	GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
637 	GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
641 	GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),