clk/mediatek/clk-mt2712.c

1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "clk-mtk.h"
17 #include "clk-gate.h"
19 #include <dt-bindings/clock/mt2712-clk.h>
39 	FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
41 	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
46 	FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
48 	FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
50 	FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
52 	FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
54 	FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
56 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
58 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
60 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
62 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
64 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
66 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
68 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
70 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
72 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
74 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
76 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
78 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
80 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
82 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
84 	FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
86 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
88 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
90 	FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
92 	FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
94 	FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
96 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
98 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
100 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
102 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
104 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
106 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
108 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
110 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
112 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
114 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
116 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
118 	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
120 	FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
122 	FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
124 	FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
126 	FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
128 	FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
130 	FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
132 	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
134 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
136 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
138 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
140 	FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
142 	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
144 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
146 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
148 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
150 	FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
152 	FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
154 	FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
156 	FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
158 	FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
160 	FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
162 	FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
164 	FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
166 	FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
168 	FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
170 	FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
172 	FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
174 	FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
176 	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
178 	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
180 	FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
182 	FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
184 	FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
186 	FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
188 	FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
190 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
192 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
194 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
196 	FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
198 	FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
200 	FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
202 	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
204 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
206 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
208 	FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
210 	FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
212 	FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
214 	FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
216 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
218 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
928 		9, 2, -1, CLK_IS_CRITICAL),
931 		9, 2, -1, CLK_IS_CRITICAL),
934 		9, 2, -1, CLK_IS_CRITICAL),
1264 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_apmixed_probe()
1273 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_apmixed_probe()
1289 			top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);  in clk_mt2712_top_init_early()
1297 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_top_init_early()
1301 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1307 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_top_probe()
1312 		pr_err("%s(): ioremap failed\n", __func__);  in clk_mt2712_top_probe()
1320 			if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))  in clk_mt2712_top_probe()
1321 				top_clk_data->clks[i] = ERR_PTR(-ENOENT);  in clk_mt2712_top_probe()
1340 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_top_probe()
1350 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_infra_probe()
1360 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_infra_probe()
1372 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_peri_probe()
1382 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_peri_probe()
1394 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_mcu_probe()
1399 		pr_err("%s(): ioremap failed\n", __func__);  in clk_mt2712_mcu_probe()
1411 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_mcu_probe()
1419 		.compatible = "mediatek,mt2712-apmixedsys",
1422 		.compatible = "mediatek,mt2712-topckgen",
1425 		.compatible = "mediatek,mt2712-infracfg",
1428 		.compatible = "mediatek,mt2712-pericfg",
1431 		.compatible = "mediatek,mt2712-mcucfg",
1443 	clk_probe = of_device_get_match_data(&pdev->dev);  in clk_mt2712_probe()
1445 		return -EINVAL;  in clk_mt2712_probe()
1449 		dev_err(&pdev->dev,  in clk_mt2712_probe()
1450 			"could not register clock provider: %s: %d\n",  in clk_mt2712_probe()
1451 			pdev->name, r);  in clk_mt2712_probe()
1459 		.name = "clk-mt2712",