Lines Matching +full:x1000 +full:- +full:ost
1 // SPDX-License-Identifier: GPL-2.0
3 * X1000 SoC CGU driver
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/x1000-cgu.h>
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
118 return -EINVAL; in x1000_otg_phy_set_rate()
121 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
123 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
126 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
128 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
134 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
135 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_enable()
144 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_disable()
145 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_disable()
153 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_is_enabled()
154 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_is_enabled()
172 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
186 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
209 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
230 /* Custom (SoC-specific) OTG PHY */
234 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
242 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
248 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
254 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
255 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
261 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
262 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
267 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
269 .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
274 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
280 .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
281 .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
286 .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
287 .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
293 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
323 .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
330 .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
337 .parents = { X1000_CLK_EXCLK, -1,
346 .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
359 .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
376 /* Gate-only clocks */
380 .parents = { X1000_CLK_AHB2, -1, -1, -1 },
386 .parents = { X1000_CLK_AHB2, -1, -1, -1 },
392 .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
398 .parents = { X1000_CLK_PCLK, -1, -1, -1 },
404 .parents = { X1000_CLK_PCLK, -1, -1, -1 },
410 .parents = { X1000_CLK_PCLK, -1, -1, -1 },
416 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
422 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
428 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
434 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
440 .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
445 "ost", CGU_CLK_GATE,
446 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
452 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
478 * in the case where the device node is compatible with "simple-mfd".
480 CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);