Lines Matching +full:29 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/jz4780-cgu.h>
53 #define OPCR_SPENDN0 BIT(7)
54 #define OPCR_SPENDN1 BIT(6)
57 #define USBPCR_USB_MODE BIT(31)
59 #define USBPCR_COMMONONN BIT(25)
60 #define USBPCR_VBUSVLDEXT BIT(24)
61 #define USBPCR_VBUSVLDEXTSEL BIT(23)
62 #define USBPCR_POR BIT(22)
63 #define USBPCR_SIDDQ BIT(21)
64 #define USBPCR_OTG_DISABLE BIT(20)
69 #define USBPCR_TXPREEMPHTUNE BIT(6)
83 #define USBPCR1_USB_SEL BIT(28)
84 #define USBPCR1_WORD_IF0 BIT(19)
85 #define USBPCR1_WORD_IF1 BIT(18)
88 #define USBRDT_VBFIL_LD_EN BIT(25)
97 #define LCR_PD_SCPU BIT(31)
98 #define LCR_SCPUS BIT(27)
101 #define CLKGR1_CORE1 BIT(15)
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
170 return -EINVAL; in jz4780_otg_phy_set_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
186 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_enable()
187 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_enable()
196 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_disable()
197 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_disable()
205 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_is_enabled()
206 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_is_enabled()
226 struct ingenic_cgu *cgu = ingenic_clk->cgu; in jz4780_core1_enable()
232 spin_lock_irqsave(&cgu->lock, flags); in jz4780_core1_enable()
234 lcr = readl(cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
236 writel(lcr, cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
238 clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); in jz4780_core1_enable()
240 writel(clkgr1, cgu->base + CGU_REG_CLKGR1); in jz4780_core1_enable()
242 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_core1_enable()
245 retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, in jz4780_core1_enable()
247 if (retval == -ETIMEDOUT) { in jz4780_core1_enable()
294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
318 /* Custom (SoC-specific) OTG PHY */
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
344 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
345 .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
350 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
351 .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
356 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
359 .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
364 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
371 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
372 .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
377 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
378 .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
383 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
385 .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
391 JZ4780_CLK_EPLL, -1 },
393 .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 },
399 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
401 .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 },
406 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
413 JZ4780_CLK_VPLL, -1 },
421 JZ4780_CLK_VPLL, -1 },
428 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
434 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
435 .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
441 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
442 .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
448 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
449 .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 },
458 .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 },
464 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
466 .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
471 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
477 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
479 .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 },
486 .mux = { CGU_REG_PCMCDR, 29, 2 },
492 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
499 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
502 .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 },
509 JZ4780_CLK_VPLL, -1 },
511 .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 },
517 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
520 .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
536 /* Gate-only clocks */
540 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
546 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
552 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
558 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
564 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
570 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
576 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
582 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
588 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
594 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
600 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
606 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
612 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
618 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
624 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
630 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
636 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
642 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
648 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
654 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
660 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
666 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
672 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
678 .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
684 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
685 .gate = { CGU_REG_CLKGR0, 29 },
690 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
696 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
702 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
708 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
714 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
720 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
726 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
732 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
738 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
744 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
750 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
756 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
762 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
768 .parents = { JZ4780_CLK_CPU, -1, -1, -1 },
793 CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);