371 	u32 div_reg, div;  in ingenic_clk_recalc_rate()  local
374 		div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
375 		div = (div_reg >> clk_info->div.shift) &  in ingenic_clk_recalc_rate()
376 		      GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_recalc_rate()
378 		if (clk_info->div.div_table)  in ingenic_clk_recalc_rate()
379 			div = clk_info->div.div_table[div];  in ingenic_clk_recalc_rate()
381 			div = (div + 1) * clk_info->div.div;  in ingenic_clk_recalc_rate()
383 		rate /= div;  in ingenic_clk_recalc_rate()
385 		rate /= clk_info->fixdiv.div;  in ingenic_clk_recalc_rate()
393 			unsigned int div)  in ingenic_clk_calc_hw_div()  argument
397 	for (i = 0; i < (1 << clk_info->div.bits)  in ingenic_clk_calc_hw_div()
398 				&& clk_info->div.div_table[i]; i++) {  in ingenic_clk_calc_hw_div()
399 		if (clk_info->div.div_table[i] >= div &&  in ingenic_clk_calc_hw_div()
400 		    clk_info->div.div_table[i] < best) {  in ingenic_clk_calc_hw_div()
401 			best = clk_info->div.div_table[i];  in ingenic_clk_calc_hw_div()
404 			if (div == best)  in ingenic_clk_calc_hw_div()
416 	unsigned int div, hw_div;  in ingenic_clk_calc_div()  local
419 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
421 	if (clk_info->div.div_table) {  in ingenic_clk_calc_div()
422 		hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_calc_div()
424 		return clk_info->div.div_table[hw_div];  in ingenic_clk_calc_div()
428 	div = clamp_t(unsigned int, div, clk_info->div.div,  in ingenic_clk_calc_div()
429 		      clk_info->div.div << clk_info->div.bits);  in ingenic_clk_calc_div()
436 	div = DIV_ROUND_UP(div, clk_info->div.div);  in ingenic_clk_calc_div()
437 	div *= clk_info->div.div;  in ingenic_clk_calc_div()
439 	return div;  in ingenic_clk_calc_div()
448 	unsigned int div = 1;  in ingenic_clk_round_rate()  local
451 		div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);  in ingenic_clk_round_rate()
453 		div = clk_info->fixdiv.div;  in ingenic_clk_round_rate()
457 	return DIV_ROUND_UP(*parent_rate, div);  in ingenic_clk_round_rate()
465 	return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,  in ingenic_clk_check_stable()
466 				  !(reg & BIT(clk_info->div.busy_bit)),  in ingenic_clk_check_stable()
478 	unsigned int hw_div, div;  in ingenic_clk_set_rate()  local
483 		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
484 		rate = DIV_ROUND_UP(parent_rate, div);  in ingenic_clk_set_rate()
489 		if (clk_info->div.div_table)  in ingenic_clk_set_rate()
490 			hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_set_rate()
492 			hw_div = ((div / clk_info->div.div) - 1);  in ingenic_clk_set_rate()
495 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
498 		mask = GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_set_rate()
499 		reg &= ~(mask << clk_info->div.shift);  in ingenic_clk_set_rate()
500 		reg |= hw_div << clk_info->div.shift;  in ingenic_clk_set_rate()
503 		if (clk_info->div.stop_bit != -1)  in ingenic_clk_set_rate()
504 			reg &= ~BIT(clk_info->div.stop_bit);  in ingenic_clk_set_rate()
507 		if (clk_info->div.ce_bit != -1)  in ingenic_clk_set_rate()
508 			reg |= BIT(clk_info->div.ce_bit);  in ingenic_clk_set_rate()
511 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
514 		if (clk_info->div.busy_bit != -1)  in ingenic_clk_set_rate()