Lines Matching refs:clk_info
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_recalc_rate() local
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
122 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, in ingenic_pll_calc() argument
129 pll_info = &clk_info->pll; in ingenic_pll_calc()
137 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); in ingenic_pll_calc()
141 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); in ingenic_pll_calc()
160 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_round_rate() local
162 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); in ingenic_pll_round_rate()
181 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_set_rate() local
182 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
188 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, in ingenic_pll_set_rate()
192 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
221 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_enable() local
222 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
250 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_disable() local
251 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
268 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_is_enabled() local
269 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
294 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_get_parent() local
299 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
300 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
301 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
302 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
309 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
320 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_parent() local
326 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
334 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
336 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
346 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
347 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
352 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
354 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
355 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
368 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_recalc_rate() local
373 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
374 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
375 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
376 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
378 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
379 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
381 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
384 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
385 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
392 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_hw_div() argument
397 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
398 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
399 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
400 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
401 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
413 ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_div() argument
421 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
422 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
424 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
428 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
429 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
436 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
437 div *= clk_info->div.div; in ingenic_clk_calc_div()
447 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_round_rate() local
450 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
451 div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate); in ingenic_clk_round_rate()
452 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_round_rate()
453 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
461 const struct ingenic_cgu_clk_info *clk_info) in ingenic_clk_check_stable() argument
465 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
466 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
475 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_rate() local
482 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
483 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
489 if (clk_info->div.div_table) in ingenic_clk_set_rate()
490 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
492 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
495 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
498 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
499 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
500 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
503 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
504 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
507 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
508 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
511 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
514 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
515 ret = ingenic_clk_check_stable(cgu, clk_info); in ingenic_clk_set_rate()
527 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_enable() local
531 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
534 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
537 if (clk_info->gate.delay_us) in ingenic_clk_enable()
538 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
547 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_disable() local
551 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
554 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
562 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_is_enabled() local
566 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
567 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
591 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock() local
599 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
601 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
602 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
605 __func__, clk_info->name); in ingenic_register_clock()
609 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
618 if (!clk_info->type) { in ingenic_register_clock()
620 clk_info->name); in ingenic_register_clock()
634 clk_init.name = clk_info->name; in ingenic_register_clock()
638 caps = clk_info->type; in ingenic_register_clock()
651 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
653 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
656 if (clk_info->parents[i] == -1) in ingenic_register_clock()
659 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
668 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
670 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
675 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
716 clk_info->name); in ingenic_register_clock()
721 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()