442 	u16 clk_val;  member
502 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_unprepare()
517 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_enable()
520 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
531 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_disable()
534 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_disable()
537 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
571 	switch (sclk->clk_val) {  in syscon_clk_recalc_rate()
638 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_round_rate()
657 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_set_rate()
698 		    u16 clk_val)  in syscon_clk_register()  argument
722 	sclk->clk_val = clk_val;  in syscon_clk_register()
749 	u16 clk_val;  member
757 		.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
763 		.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
769 		.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
775 		.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
781 		.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
787 		.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
793 		.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
800 		.clk_val = 0xFFFFU,
806 		.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
812 		.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
818 		.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
824 		.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
830 		.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
836 		.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
842 		.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
848 		.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
855 		.clk_val = 0xFFFFU,
861 		.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
867 		.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
920 						 u3clk->clk_val);  in of_u300_syscon_clk_init()