319 	void *cfg;  member
323 				const struct clock_config *cfg);
383 		      const struct clock_config *cfg)  in _clk_hw_register_gate()  argument
385 	struct gate_cfg *gate_cfg = cfg->cfg;  in _clk_hw_register_gate()
388 				    cfg->name,  in _clk_hw_register_gate()
389 				    cfg->parent_name,  in _clk_hw_register_gate()
390 				    cfg->flags,  in _clk_hw_register_gate()
401 			      const struct clock_config *cfg)  in _clk_hw_register_fixed_factor()  argument
403 	struct fixed_factor_cfg *ff_cfg = cfg->cfg;  in _clk_hw_register_fixed_factor()
405 	return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,  in _clk_hw_register_fixed_factor()
406 					    cfg->flags, ff_cfg->mult,  in _clk_hw_register_fixed_factor()
414 			       const struct clock_config *cfg)  in _clk_hw_register_divider_table()  argument
416 	struct div_cfg *div_cfg = cfg->cfg;  in _clk_hw_register_divider_table()
419 					     cfg->name,  in _clk_hw_register_divider_table()
420 					     cfg->parent_name,  in _clk_hw_register_divider_table()
421 					     cfg->flags,  in _clk_hw_register_divider_table()
434 		     const struct clock_config *cfg)  in _clk_hw_register_mux()  argument
436 	struct mux_cfg *mux_cfg = cfg->cfg;  in _clk_hw_register_mux()
438 	return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,  in _clk_hw_register_mux()
439 				   cfg->num_parents, cfg->flags,  in _clk_hw_register_mux()
473 				     const struct stm32_mux_cfg *cfg,  in _get_stm32_mux()  argument
480 	if (cfg->mmux) {  in _get_stm32_mux()
485 		mmux->mux.reg = cfg->mux->reg_off + base;  in _get_stm32_mux()
486 		mmux->mux.shift = cfg->mux->shift;  in _get_stm32_mux()
487 		mmux->mux.mask = (1 << cfg->mux->width) - 1;  in _get_stm32_mux()
488 		mmux->mux.flags = cfg->mux->mux_flags;  in _get_stm32_mux()
489 		mmux->mux.table = cfg->mux->table;  in _get_stm32_mux()
491 		mmux->mmux = cfg->mmux;  in _get_stm32_mux()
493 		cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;  in _get_stm32_mux()
500 		mux->reg = cfg->mux->reg_off + base;  in _get_stm32_mux()
501 		mux->shift = cfg->mux->shift;  in _get_stm32_mux()
502 		mux->mask = (1 << cfg->mux->width) - 1;  in _get_stm32_mux()
503 		mux->flags = cfg->mux->mux_flags;  in _get_stm32_mux()
504 		mux->table = cfg->mux->table;  in _get_stm32_mux()
513 				     const struct stm32_div_cfg *cfg,  in _get_stm32_div()  argument
523 	div->reg = cfg->div->reg_off + base;  in _get_stm32_div()
524 	div->shift = cfg->div->shift;  in _get_stm32_div()
525 	div->width = cfg->div->width;  in _get_stm32_div()
526 	div->flags = cfg->div->div_flags;  in _get_stm32_div()
527 	div->table = cfg->div->table;  in _get_stm32_div()
535 		const struct stm32_gate_cfg *cfg, spinlock_t *lock)  in _get_stm32_gate()  argument
541 	if (cfg->mgate) {  in _get_stm32_gate()
546 		mgate->gate.reg = cfg->gate->reg_off + base;  in _get_stm32_gate()
547 		mgate->gate.bit_idx = cfg->gate->bit_idx;  in _get_stm32_gate()
548 		mgate->gate.flags = cfg->gate->gate_flags;  in _get_stm32_gate()
550 		mgate->mask = BIT(cfg->mgate->nbr_clk++);  in _get_stm32_gate()
552 		mgate->mgate = cfg->mgate;  in _get_stm32_gate()
561 		gate->reg = cfg->gate->reg_off + base;  in _get_stm32_gate()
562 		gate->bit_idx = cfg->gate->bit_idx;  in _get_stm32_gate()
563 		gate->flags = cfg->gate->gate_flags;  in _get_stm32_gate()
578 			    const struct stm32_gate_cfg *cfg,  in clk_stm32_register_gate_ops()  argument
592 	if (cfg->ops)  in clk_stm32_register_gate_ops()
593 		init.ops = cfg->ops;  in clk_stm32_register_gate_ops()
595 	hw = _get_stm32_gate(base, cfg, lock);  in clk_stm32_register_gate_ops()
612 			     const struct stm32_composite_cfg *cfg,  in clk_stm32_register_composite()  argument
625 	if (cfg->mux) {  in clk_stm32_register_composite()
626 		mux_hw = _get_stm32_mux(base, cfg->mux, lock);  in clk_stm32_register_composite()
631 			if (cfg->mux->ops)  in clk_stm32_register_composite()
632 				mux_ops = cfg->mux->ops;  in clk_stm32_register_composite()
636 	if (cfg->div) {  in clk_stm32_register_composite()
637 		div_hw = _get_stm32_div(base, cfg->div, lock);  in clk_stm32_register_composite()
642 			if (cfg->div->ops)  in clk_stm32_register_composite()
643 				div_ops = cfg->div->ops;  in clk_stm32_register_composite()
647 	if (cfg->gate) {  in clk_stm32_register_composite()
648 		gate_hw = _get_stm32_gate(base, cfg->gate, lock);  in clk_stm32_register_composite()
653 			if (cfg->gate->ops)  in clk_stm32_register_composite()
654 				gate_ops = cfg->gate->ops;  in clk_stm32_register_composite()
1041 					const struct clock_config *cfg)  in _clk_register_pll()  argument
1043 	struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;  in _clk_register_pll()
1045 	return clk_register_pll(dev, cfg->name, cfg->parent_name,  in _clk_register_pll()
1046 				base + stm_pll_cfg->offset, cfg->flags, lock);  in _clk_register_pll()
1057 					  const struct clock_config *cfg)  in _clk_register_cktim()  argument
1059 	struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;  in _clk_register_cktim()
1061 	return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,  in _clk_register_cktim()
1070 			 const struct clock_config *cfg)  in _clk_stm32_register_gate()  argument
1073 				    cfg->name,  in _clk_stm32_register_gate()
1074 				    cfg->parent_name,  in _clk_stm32_register_gate()
1075 				    cfg->flags,  in _clk_stm32_register_gate()
1077 				    cfg->cfg,  in _clk_stm32_register_gate()
1085 			      const struct clock_config *cfg)  in _clk_stm32_register_composite()  argument
1087 	return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,  in _clk_stm32_register_composite()
1088 					    cfg->num_parents, base, cfg->cfg,  in _clk_stm32_register_composite()
1089 					    cfg->flags, lock);  in _clk_stm32_register_composite()
1098 	.cfg		=  &(struct gate_cfg) {\
1112 	.cfg		=  &(struct fixed_factor_cfg) {\
1126 	.cfg		=  &(struct div_cfg) {\
1147 	.cfg		=  &(struct mux_cfg) {\
1162 	.cfg		=  &(struct stm32_pll_cfg) {\
1174 	.cfg		=  &(struct stm32_cktim_cfg) {\
1192 	.cfg		= (struct stm32_gate_cfg *) {_gate},\
1277 	.cfg		= &(struct stm32_composite_cfg) {\
2000 	const struct clock_config *cfg;  member
2006 	.cfg		= stm32mp1_clock_cfg,
2022 				 const struct clock_config *cfg)  in stm32_register_hw_clk()  argument
2029 	if (cfg->func)  in stm32_register_hw_clk()
2030 		hw = (*cfg->func)(dev, clk_data, base, lock, cfg);  in stm32_register_hw_clk()
2033 		pr_err("Unable to register %s\n", cfg->name);  in stm32_register_hw_clk()
2037 	if (cfg->id != NO_ID)  in stm32_register_hw_clk()
2038 		hws[cfg->id] = hw;  in stm32_register_hw_clk()
2077 					    &data->cfg[n]);  in stm32_rcc_init()
2080 			       data->cfg[n].name);  in stm32_rcc_init()